- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 25kb
- Update:
- 2018-04-21
- Downloads:
- 0 Times
- Uploaded by:
- 韩冻少
Description: FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| FIR设计实现sgh\Coe.xlsx | 10187 | 2016-12-29
|
| FIR设计实现sgh\FIRdesign.m | 8935 | 2017-01-16
|
| FIR设计实现sgh\FirParallel.v | 10137 | 2017-01-16
|
| FIR设计实现sgh\FIR滤波器设计指南.docx | 14512 | 2017-01-16
|
| FIR设计实现sgh\~$R滤波器设计指南.docx | 162 | 2017-01-16
|
| FIR设计实现sgh | 0 | 2017-01-16 |
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