ed_synth_17_0_0_290 The DDR4 on A10 FPGA is initia

Title: ed_synth_17_0_0_290

Description: The DDR4 on A10 FPGA is initialized and debugged.

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Filename Size Date
ed_synth_17_0_0_290.qar  1415157  2018-06-20

Filename	Size	Date
ed_synth_17_0_0_290.qar	1415157	2018-06-20

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