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Title: DDR_sdram Download
 Description: The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.
 Downloaders recently: [More information of uploader maxw123456789]
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FilenameSizeDate
DDR_sdram\1_DDR3 SDRAM Verilog Model\1024Mb_ddr3_parameters.vh 54986  2015-08-21

DDR_sdram\1_DDR3 SDRAM Verilog Model\2048Mb_ddr3_parameters.vh 54042  2015-08-21

DDR_sdram\1_DDR3 SDRAM Verilog Model\4096Mb_ddr3_parameters.vh 54042  2015-08-21

DDR_sdram\1_DDR3 SDRAM Verilog Model\8192Mb_ddr3_parameters.vh 38899  2015-08-21

DDR_sdram\1_DDR3 SDRAM Verilog Model\ddr3.v 165396  2015-09-10

DDR_sdram\1_DDR3 SDRAM Verilog Model\ddr3_dimm.v 17369  2015-06-20

DDR_sdram\1_DDR3 SDRAM Verilog Model\ddr3_mcp.v 4213  2015-06-20

DDR_sdram\1_DDR3 SDRAM Verilog Model\ddr3_module.v 34845  2015-06-20

DDR_sdram\1_DDR3 SDRAM Verilog Model\readme.txt 9421  2015-06-20

DDR_sdram\1_DDR3 SDRAM Verilog Model\subtest.vh 14463  2015-06-20

DDR_sdram\1_DDR3 SDRAM Verilog Model\tb.v 20002  2015-06-20

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\arch_defines.v 865  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\arch_package.sv 54616  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\ddr4_model.svp 184493  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\dimm.vh 1952  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\dimm_interface.sv 32365  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\dimm_subtest.vh 14415  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\dimm_tb.sv 46777  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\interface.sv 966  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\MemoryArray.svp 21148  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\memory_file.txt 1292  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\modelsim.do 2197  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\modelsim_dimm.do 2223  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\proj_package.sv 18159  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\readme.txt 5470  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\readme_dimm.txt 4249  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\run_modelsim 21  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\StateTable.svp 4963  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\StateTableCore.svp 206293  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\subtest.vh 17747  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\tb.sv 26341  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_modelsim\timing_tasks.sv 22729  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\arch_defines.v 865  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\arch_package.sv 54616  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\ddr4_model.svp 188871  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\dimm.vh 1952  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\dimm_interface.sv 32365  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\dimm_subtest.vh 14415  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\dimm_tb.sv 46777  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\interface.sv 966  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\MemoryArray.svp 21438  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\memory_file.txt 1292  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\proj_package.sv 18159  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\readme.txt 5470  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\readme_dimm.txt 4249  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\run_dimm_ncverilog 181  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\run_ncverilog 171  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\StateTable.svp 6263  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\StateTableCore.svp 206578  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\subtest.vh 17747  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\tb.sv 26341  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog\timing_tasks.sv 22729  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\arch_defines.v 865  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\arch_package.sv 54616  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\ddr4_model.svp 178263  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\dimm.vh 1952  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\dimm_interface.sv 32365  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\dimm_subtest.vh 14415  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\dimm_tb.sv 46777  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\interface.sv 966  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\MemoryArray.svp 20161  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\memory_file.txt 1292  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\proj_package.sv 18159  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\readme.txt 5470  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\readme_dimm.txt 4249  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\run_dimm_vcs 171  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\run_vcs 161  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\StateTable.svp 4316  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\StateTableCore.svp 204565  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\subtest.vh 17747  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\tb.sv 26341  2016-04-05

DDR_sdram\2_ddr4_verilog_models\protected_vcs\timing_tasks.sv 22729  2016-04-05

DDR_sdram\eetop.cn_ddr4.pdf 4622797  2018-07-12

DDR_sdram\2_ddr4_verilog_models\protected_modelsim 0  2018-07-18

DDR_sdram\2_ddr4_verilog_models\protected_ncverilog 0  2018-07-18

DDR_sdram\2_ddr4_verilog_models\protected_vcs 0  2018-07-18

DDR_sdram\1_DDR3 SDRAM Verilog Model 0  2018-07-18

DDR_sdram\2_ddr4_verilog_models 0  2018-07-18

DDR_sdram 0  2018-07-18

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