Description: RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.
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| Filename | Size | Date |
|---|
| 0ac6bf9be5f4f8397300f27dc9bdb922 | 430080 | 2018-10-24 |
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