Description: Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data will be_ In as the lowest bit of the register, the original highest bit of the register will be discarded. It is required to output the remainder data of the 16 bit register to 7 in real-time in each cycle_ out[20].
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| Filename | Size | Date |
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| lab2\lab2.docx | 477353 | 2020-05-16
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| lab2\lab2.v | 1973 | 2020-05-07
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| lab2\lab2_tb.v | 698 | 2020-05-07 |
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