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- VHDL-FPGA-Verilog
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- 2019-05-03
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Description: Design a 1MHz FIR low pass filter.
Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence.
The elements of the sequence are the 10 Numbers [0-9], each of which corresponds to a 4-bit binary representation.
Let's say 5 is equal to 0101, and 9 is equal to 1001.
The length of the input data sequence is 256.
First output the encoding of each element, and then output the data sequence corresponding Huffman coding sequence.
Requirements:
(1) clock signal frequency 16MHz;
(2) input signal bit width of 8bits, symbol rate of 16MHz
Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient
(4) write the test simulation program.
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| Filename | Size | Date |
|---|
| 哈夫曼编码器设计实验报告.docx | 225363 | 2018-06-20 |
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