Filename
Size
Date
DC Synopsys Workshop(PPT)
 0 
 2020-11-28
DC Synopsys Workshop(PPT)\DC1_200703_SG_01_intro.ppt
 523776 
 2007-03-15
DC Synopsys Workshop(PPT)\DC1_200703_SG_02_setup.ppt
 578048 
 2007-03-15
DC Synopsys Workshop(PPT)\DC1_200703_SG_03_objects.ppt
 288256 
 2007-03-15
DC Synopsys Workshop(PPT)\DC1_200703_SG_04_area_timing.ppt
 1817600 
 2015-12-22
DC Synopsys Workshop(PPT)\DC1_200703_SG_05_partitioning.ppt
 1276416 
 2015-12-23
DC Synopsys Workshop(PPT)\DC1_200703_SG_06_env.ppt
 1125888 
 2015-12-23
DC Synopsys Workshop(PPT)\DC1_200703_SG_07_compile.ppt
 2807808 
 2015-12-24
DC Synopsys Workshop(PPT)\DC1_200703_SG_08_timing_analysis.ppt
 681984 
 2007-03-20
DC Synopsys Workshop(PPT)\DC1_200703_SG_09_addl_constr.ppt
 896512 
 2007-03-15
DC Synopsys Workshop(PPT)\DC1_200703_SG_10_multiclock.ppt
 481280 
 2007-03-14
DC Synopsys Workshop(PPT)\DC1_200703_SG_11_addl_comp_tech.ppt
 1007104 
 2007-04-02
DC Synopsys Workshop(PPT)\DC1_200703_SG_12_output_data.ppt
 286208 
 2007-03-20
DC Synopsys Workshop(PPT)\DC1_200703_SG_13_conclusion.ppt
 518656 
 2007-03-15
workshop
 0 
 2020-11-28
workshop\DC1_2007.03
 0 
 2020-11-28
workshop\DC1_2007.03\.setup.modules
 209 
 2007-04-03
workshop\DC1_2007.03\.TestMaster
 0 
 2015-11-28
workshop\DC1_2007.03\.testscript
 3792 
 2007-04-03
workshop\DC1_2007.03\lab10
 0 
 2020-11-28
workshop\DC1_2007.03\lab10\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab10\.solutions\exceptions.sdc
 4011 
 2007-03-22
workshop\DC1_2007.03\lab10\.solutions\run.tcl
 957 
 2007-03-22
workshop\DC1_2007.03\lab10\.synopsys_dc.setup
 1360 
 2007-03-22
workshop\DC1_2007.03\lab10\exceptions.ddc
 118784 
 2007-03-22
workshop\DC1_2007.03\lab11
 0 
 2020-11-28
workshop\DC1_2007.03\lab11\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab11\.solutions\run.tcl
 894 
 2007-03-23
workshop\DC1_2007.03\lab11\.solutions\run_w_check_expl.tcl
 8225 
 2007-03-26
workshop\DC1_2007.03\lab11\.synopsys_dc.setup
 1366 
 2007-03-22
workshop\DC1_2007.03\lab11\mapped
 0 
 2015-11-28
workshop\DC1_2007.03\lab11\rtl
 0 
 2020-11-28
workshop\DC1_2007.03\lab11\rtl\stoto.v
 4383 
 2007-03-22
workshop\DC1_2007.03\lab11\scripts
 0 
 2020-11-28
workshop\DC1_2007.03\lab11\scripts\stoto.con
 934 
 2007-03-22
workshop\DC1_2007.03\lab2
 0 
 2020-11-28
workshop\DC1_2007.03\lab2\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab2\.solutions\.synopsys_dc.setup
 1566 
 2007-03-22
workshop\DC1_2007.03\lab2\.solutions\run_history.tcl
 299 
 2007-03-30
workshop\DC1_2007.03\lab2\.synopsys_dc.setup
 1509 
 2007-03-22
workshop\DC1_2007.03\lab2\make_alib
 40 
 2007-03-22
workshop\DC1_2007.03\lab2\mapped
 0 
 2015-11-28
workshop\DC1_2007.03\lab2\rtl
 0 
 2020-11-28
workshop\DC1_2007.03\lab2\rtl\TOP.vhd
 8463 
 2007-03-22
workshop\DC1_2007.03\lab2\scripts
 0 
 2020-11-28
workshop\DC1_2007.03\lab2\scripts\create_alib.tcl
 157 
 2007-03-22
workshop\DC1_2007.03\lab2\scripts\TOP.con
 760 
 2007-03-22
workshop\DC1_2007.03\lab2\unmapped
 0 
 2015-11-28
workshop\DC1_2007.03\lab4
 0 
 2020-11-28
workshop\DC1_2007.03\lab4\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab4\.solutions\lab4.con
 4132 
 2007-04-03
workshop\DC1_2007.03\lab4\.solutions\lab4.wscr
 3106 
 2007-04-03
workshop\DC1_2007.03\lab4\.solutions\run.tcl
 609 
 2007-04-03
workshop\DC1_2007.03\lab4\.synopsys_dc.setup
 1368 
 2007-03-22
workshop\DC1_2007.03\lab4\rtl
 0 
 2020-11-28
workshop\DC1_2007.03\lab4\rtl\my_design.v
 1171 
 2007-03-22
workshop\DC1_2007.03\lab4\scripts
 0 
 2015-11-28
workshop\DC1_2007.03\lab4\unmapped
 0 
 2015-11-28
workshop\DC1_2007.03\lab5
 0 
 2020-11-28
workshop\DC1_2007.03\lab5\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab5\.solutions\run.tcl
 235 
 2007-03-22
workshop\DC1_2007.03\lab5\.synopsys_dc.setup
 1360 
 2007-03-29
workshop\DC1_2007.03\lab5\mapped
 0 
 2020-11-28
workshop\DC1_2007.03\lab5\mapped\TOP.ddc
 36352 
 2007-04-02
workshop\DC1_2007.03\lab5\scripts
 0 
 2020-11-28
workshop\DC1_2007.03\lab5\scripts\TOP.con
 665 
 2007-03-22
workshop\DC1_2007.03\lab5\unmapped
 0 
 2020-11-28
workshop\DC1_2007.03\lab5\unmapped\TOP.ddc
 35584 
 2007-04-02
workshop\DC1_2007.03\lab6
 0 
 2020-11-28
workshop\DC1_2007.03\lab6\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab6\.solutions\lab6.con
 5246 
 2007-03-22
workshop\DC1_2007.03\lab6\.solutions\lab6.wscr
 5717 
 2007-04-03
workshop\DC1_2007.03\lab6\.solutions\run.tcl
 512 
 2007-03-22
workshop\DC1_2007.03\lab6\.synopsys_dc.setup
 1367 
 2007-03-22
workshop\DC1_2007.03\lab6\rtl
 0 
 2020-11-28
workshop\DC1_2007.03\lab6\rtl\my_design.v
 1171 
 2007-03-22
workshop\DC1_2007.03\lab6\scripts
 0 
 2015-11-28
workshop\DC1_2007.03\lab6\unmapped
 0 
 2015-11-28
workshop\DC1_2007.03\lab9
 0 
 2020-11-28
workshop\DC1_2007.03\lab9\.solutions
 0 
 2020-11-28
workshop\DC1_2007.03\lab9\.solutions\lab9A.con
 8303 
 2007-03-22
workshop\DC1_2007.03\lab9\.solutions\lab9A.wscr
 13482 
 2007-04-03
workshop\DC1_2007.03\lab9\.solutions\run9A.tcl
 762 
 2007-03-22
workshop\DC1_2007.03\lab9\.synopsys_dc.setup
 1375 
 2007-03-22
workshop\DC1_2007.03\lab9\mapped
 0 
 2020-11-28
workshop\DC1_2007.03\lab9\mapped\ISOLATE_PORTS.ddc
 13824 
 2007-03-22
workshop\DC1_2007.03\lab9\rtl
 0 
 2020-11-28
workshop\DC1_2007.03\lab9\rtl\my_design.v
 1171 
 2007-03-22
workshop\DC1_2007.03\lab9\scripts
 0 
 2020-11-28
workshop\DC1_2007.03\lab9\scripts\isolate_ports.con
 275 
 2007-03-22
workshop\DC1_2007.03\README
 3775 
 2007-04-03
workshop\DC1_2007.03\ref
 0 
 2020-11-28
workshop\DC1_2007.03\ref\db
 0 
 2020-11-28
workshop\DC1_2007.03\ref\db\sc.sdb
 437731 
 2007-03-22
workshop\DC1_2007.03\ref\db\sc_max.db
 4453603 
 2007-03-22
workshop\DC1_2007.03\ref\db\sc_min.db
 4401067 
 2007-03-22
workshop\DC1_2007.03\ref\dc_settings.tcl
 1356 
 2007-03-22
workshop\DC1_2007.03\ref\tools
 0 
 2020-11-28
workshop\DC1_2007.03\ref\tools\procs.tcl
 5713 
 2007-03-22
workshop\DC1_2007.03\ref\tools\README
 421 
 2007-03-22