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Title:
一些VHDL源代码
Download
Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
44.05kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
babylune
Description:
within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Downloaders recently:
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More information of uploader babylune
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To Search:
fifo
ram vhdl
VHDL
fifo vhdl
ram vhdl
ram
fifo 8 8
fifo 16 8
[
DSPapplicationswithexamples:TMS320LF2407(EV
] - DSP applications with examples : TMS320L
[
eightpseudo-randomnumbergeneratorinVerilogd
] - eight pseudo-random number generator in
[
eightAdder.Rar
] - Adder eight of the original code, read t
[
asinewavegeneratorandthewaveformgenerator.
] - This is a typical wave generator Shogen
[
muxplusii--VHDLclassicprocedures.Rar
] - prepared using VHDL digital clock, Varia
[
ddfs
] - my own use VHDL to achieve series dds, a
[
fpq
] - This paper introduces the application of
[
signal
] - VHDL-based multi-language source wavefor
[
fifo-1117
] - This is the asynchronous FIFO realize th
[
asyn_FIFOrealizedbyVHDL
] - A more classic FIFO paper with VHDL impl
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