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Title:
八位的伪随机数产生的verilog文件
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Category:
VHDL-FPGA-Verilog
Tags:
[Text]
File Size:
1.79kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
czhengyi
Description:
eight pseudo-random number generator in Verilog document linear-feedback- shift-register
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