Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - 分频器

Search list

[Other resource] 基于CPLD-FPGA的半整数分频器的设计

Description: 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
Platform: | Size: 21359 | Author: 胡路听 | Hits:

[Other resource] 分频器FENPIN1

Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time - with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
Platform: | Size: 3131 | Author: 李培 | Hits:

[Documents] 分频器

Description: 详细分析了各种分频器以及其算法，还有举例！
Platform: | Size: 12621 | Author: luyuang@126.com | Hits:

[VHDL-FPGA-Verilog] 数控分频器

Description: 数控分频器，可自主选择分频系数
Platform: | Size: 436 | Author: 798291651@qq.com | Hits:

[Other] 分频器

Description: 通用分频器 +仿真
Platform: | Size: 260479 | Author: carl413 | Hits:

[Documents]  分频器VHDL语言讲解.doc

Description: 分频器VHDL语言讲解
Platform: | Size: 28160 | Author: aqw123456789@21cn.com | Hits:

[VHDL-FPGA-Verilog] 分频器设计

Description: 设计一个带复位的分频器，输入时钟为60MHz，输出时钟为7.5MHz。
Platform: | Size: 54224 | Author: 197363314@qq.com | Hits:

[Documents] 数字钟的设计

Description: 数字式计时器一般都由震荡器，分频器，译码器及显示几部分组成。其中震荡器和分频器组成标准秒信号发生器，接成各种不同进制的计数器组成计时系统，译码器，显示器组成显示系统，另外一些组合电路组成校时调节系统。-digital timer usually are oscillator, dividers, decoder and display several parts. Which oscillator and divider standard component signal generator seconds, then into a variety of counter-band component metering systems, decoder, display composition display system, some other combination of circuit composed of school-conditioning system.
Platform: | Size: 118784 | Author: lee | Hits:

[VHDL-FPGA-Verilog] fen

Description: verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2
Platform: | Size: 153600 | Author: 搞广鹤 | Hits:

[VHDL-FPGA-Verilog] fpq128

Description: 自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,
Platform: | Size: 3072 | Author: 安德森 | Hits:

[VHDL-FPGA-Verilog] 分频器FENPIN1

Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
Platform: | Size: 3072 | Author: 李培 | Hits:

[VHDL-FPGA-Verilog] 基于CPLD-FPGA的半整数分频器的设计

Description: 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
Platform: | Size: 21504 | Author: 胡路听 | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[Other Embeded program] counter_7seg

Description: 带分频器的bcd计数电路设计，verilog源码-dividers with the bcd count circuit design, Verilog source
Platform: | Size: 292864 | Author: 倪璠 | Hits:

[VHDL-FPGA-Verilog] FPGAprogram2

Description: 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
Platform: | Size: 3072 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] digitalsystemDesign

Description: 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer
Platform: | Size: 446464 | Author: 李唐 | Hits:

[Windows Develop] 预置分频器

Description: FPGA预置分频器，实现各分频功能。。。。。。。。(FPGA preset divider)
Platform: | Size: 186368 | Author: 厘米limi | Hits:

[VHDL-FPGA-Verilog] vhdl分频器设计

Description: vhdl分频器设计，用quartus软件偏写，可进行时钟的分频。(Design of VHDL frequency divider)
Platform: | Size: 279552 | Author: YXT800 | Hits:

[VHDL-FPGA-Verilog] 分频器

Description: 一个简单的数字分频器，用于eda实验，电子技术综合实验(Digital frequency divider)
Platform: | Size: 10240 | Author: 左城梦 | Hits:

[VHDL-FPGA-Verilog] 分频器

Description: 对频率实现分频，达到一种对外部的一种分频管理(realization of frequency division)
Platform: | Size: 8192 | Author: MATLAB难啊 | Hits:
« 12 3 4 5 6 7 8 9 10 ... 45 »

CodeBus www.codebus.net