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Description: 这是一个在51单片机上用汇编实现的除法程序。-This one of the 51 Series MCU used to achieve the division procedures.
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Size: 825 |
Author: 杨海 |
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Description: 16位二进制PIC除法子程序-16 binary division subroutine PIC
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Size: 2037 |
Author: 汪峰 |
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Description: 基于５１单片机的３２位除法程序-based on the 32-bit microcontroller division procedures
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Size: 1354 |
Author: 刘役 |
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Description: ;-----------------------------------------------
;多字节十进制除法子程序CDIV
;入口：RO指向被除数2n字节压缩BCD码高位，
;R1指向除数n字节压缩BCD码高位，R3=n
;结果：商数压缩BCD码放入R0~(R0+2n)指向的2n个字节中，
;余数压缩BCD码放入(R0-n)~R0指向的n个字节中
;使用A，R0，R1，R2，R3，R4，R6，R7，影响CY，CY=1结果溢出
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Size: 972 |
Author: lzw72@sohu.com |
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Description: 16位二进制PIC除法子程序-16 binary division subroutine PIC
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Size: 2048 |
Author: 汪峰 |
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Description: 基于５１单片机的３２位除法程序-based on the 32-bit microcontroller division procedures
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Size: 1024 |
Author: 刘役 |
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Description: 32比特整数与16比特整数相除的一种方法-32-bit integer and 16-bit integer eliminate a method
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Size: 6144 |
Author: 小方 |
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Description: 多位数除法程序，满足在单片机编程中对除法程序的需要，解决了单片机指令无除法程序的缺点，而且本程序不限制位数。-over the median divider, which meets in MCU Programming division procedures to the needs of SCM solutions division procedures directive without shortcomings, but the procedure does not limit the median.
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Size: 4096 |
Author: 方丹 |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。
其实现方法是，将除法器分为两个状态：等待状态与运算状态。
开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
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Size: 82944 |
Author: aa |
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Description: MCU加、减、乘、除法,包含单字节到多字节，可直接调用-MCU, plus or minus, multiplication and division, including more single-byte to byte can be called directly
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Size: 6144 |
Author: |
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Description: 实现二进制定点运算:
1.定点整数补码加法
2.定点整数补码减法
3.定点小数Booth补码一位乘法
4.定点小数原码一位除法（加减交替法）
5.定点小数补码一位除法（加减交替法）
6.定点小数原码一位乘法
7.定点小数原码两位乘法
8.定点整数原码乘法
9.定点整数原码除法-achieve binary fixed point operations : 1. Sentinel integral complement Adder 2. Sentinel integral complement subtraction 3. Sentinel minority Booth complement a multiplication 4. Sentinel a few original code division (Modified alternate) 5. Sentinel minority complement one division (Modified alternate) 6 . sentinel decimal multiplication an original seven yards. sentinel original code two decimal multiplication 8. sentinel integer multiplication original nine yards. sentinel Integer original code division
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Size: 359424 |
Author: 陈婷 |
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Description: 这是一个在51单片机上用汇编实现的除法程序。-This one of the 51 Series MCU used to achieve the division procedures.
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Size: 1024 |
Author: 杨海 |
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Description: 一种实用的单片机多字节除法算法以及实现的汇编源代码。稍加改动就能作为子程序调用。相对实用。-a practical multi-byte microcontroller division algorithm and the realization of the compilation of source code. Little changes can serve as a subroutine call. Relative practical.
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Size: 4096 |
Author: 王海 |
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Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
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Size: 741376 |
Author: lele |
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Description: 适用于单片机自己编写的汇编程序，考虑了双字节可进行4舍五入的除法，完全版，通过验证。-apply to the preparation of a compilation of their own procedures, consider the double byte can be four to five homes in the division, Complete, through certification.
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Size: 1024 |
Author: 刘雁 |
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Description: div24_16
8051 div24_16 除法源碼-div24_16 8051 div24_16 division FOSS
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Size: 1024 |
Author: |
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Description: 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
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Size: 7168 |
Author: |
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Description: 通过背景减除法实现目标与背景的分离，并且可以对单目标进行跟踪(The background subtraction method is used to separate the target from the background, and the single target can be tracked)
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Size: 7075840 |
Author: 蓝言
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Description: 说明了verilog中如何处理符号数的除法(verilog signed divided)
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Size: 1024 |
Author: hunter.he
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