Search - 32位除法器

Search - 32位除法器 - List

[Other resource] div2 DL : 2: 32位除法器被除数和除数均为16位整数，16位小数商为32位整数，16位小数余数为16位整数，16位小数 Verilog HDL 代码
Date : 2008-10-13 Size : 1.49kb User : 李春阳
[Other] testbench DL : 0: 32位除法器的测试程序，由随机向量产生函数产生一组随机数来验证计算书否正确
Date : 2008-10-13 Size : 5.53kb User : 李春阳
[Other resource] divider DL : 0: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。
Date : 2008-10-13 Size : 2.27kb User : 朱秋玲
[Other resource] 32divider DL : 0: 32位元2進位除法器
Date : 2008-10-13 Size : 1.83kb User : chen
[Windows Develop] div2 32位除法器 DL : 0: ：32位除法器被除数和除数均为16位整数，16位小数商为32位整数，16位小数余数为16位整数，16位小数 Verilog HDL 代码-32
Date : 2011-09-01 Size : 1.5kb User : hyh110120119@163.com
[SourceCode] 除法器verilog DL : 0: 32位除法器，verilog编写
Date : 2012-01-03 Size : 1.5kb User : mhdmhdys@126.com
[VHDL-FPGA-Verilog] div2 DL : 0: 32位除法器被除数和除数均为16位整数，16位小数商为32位整数，16位小数余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Date : 2025-07-06 Size : 1kb User : 李春阳
[Other] testbench DL : 0: 32位除法器的测试程序，由随机向量产生函数产生一组随机数来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
Date : 2025-07-06 Size : 5kb User : 李春阳
[VHDL-FPGA-Verilog] divider DL : 1: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Date : 2025-07-06 Size : 2kb User : 朱秋玲
[VHDL-FPGA-Verilog] divider DL : 0: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Date : 2025-07-06 Size : 3kb User : 刘蒲霞
[VHDL-FPGA-Verilog] 32divider DL : 0: 32位元2進位除法器 -32-bit binary divider 2
Date : 2025-07-06 Size : 2kb User : chen
[VHDL-FPGA-Verilog] div(FLP) DL : 0: 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除-Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Date : 2025-07-06 Size : 18kb User : TTJ
[VHDL-FPGA-Verilog] fpga_chufaqi DL : 0: 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
Date : 2025-07-06 Size : 259kb User : 贾恒龙
[VHDL-FPGA-Verilog] divider DL : 0: FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
Date : 2025-07-06 Size : 1kb User : 余木
[VHDL-FPGA-Verilog] chufaqi DL : 0: 介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。-A programmable logic device FPGA and VHDL design of the 32 divider. The divider can be achieved not only symbolic arithmetic, unsigned op.
Date : 2025-07-06 Size : 2kb User : guoting
[VHDL-FPGA-Verilog] divider_32bitdivby16bit DL : 0: verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
Date : 2025-07-06 Size : 1kb User : jiang
[VHDL-FPGA-Verilog] con_addr_32 DL : 0: 因为二进制加法的进位只可能是1或0，所以可以将32位加法器分为8块（最低一块由4位先行进位加法器直接构成，其余加法结构都采用先行进位加法器结构）分别进行加法计算，除最低位以外的其他7块加法器结构各复制两份，进位输入分别预定为1和0。于是，8块加法器可以同时进行各自的加法运算，然后根据各自相邻低位加法运算结果产生的进位输出，选择正确的加法结果输出。-Because binary adder carry only be 1 or 0, so it can be 32-bit adder is divided into eight (minimum one by the four carry-lookahead adder directly constitute the remaining adder structures using carry-lookahead adder structure), respectively Addition calculation, in addition to other than the lowest seven two copies of each adder structure, carry input is scheduled for 1 and 0, respectively. Thus, the adder 8 can be performed simultaneously the respective adder, and then the respective adjacent low addition result generated carry bit output, select the correct output of the addition result.
Date : 2025-07-06 Size : 2kb User : Peter
[VHDL-FPGA-Verilog] 32-bit-division-design-In-Verilog DL : 0: 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
Date : 2025-07-06 Size : 1kb User : yangd
[VHDL-FPGA-Verilog] DIV DL : 0: 最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider dividend divisor* quotient+ remainder //dividend 32 bit //divisor 16 bit //quotient 32 bit //remainder 32 bit //need 32 clk to finish the calculation //start 1 start the calculation //start 0 keep the reset //when finished, sample 1, and the result will be keep until start 0
Date : 2025-07-06 Size : 1kb User : 顺星
[Embeded-SCM Develop] DIV DL : 0: 将两个32 有符号数相除，得到一个32 位商和余数，其中余数符号与被除数符号相同。(Two 32 Division has a number of symbols, get a 32 bit quotient and remainder, the remainder with the same divisor symbol symbol.)
Date : 2025-07-06 Size : 1kb User : SunFlowers_chao

« 12 »