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[VHDL-FPGA-Verilog] adder_32

Description: 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[Windows Develop] adder

Description: 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
Platform: | Size: 36864 | Author: sigma | Hits:

[VHDL-FPGA-Verilog] hw5

Description: 32-bit adder CLA, CSKA adder
Platform: | Size: 894976 | Author: simge | Hits:

[ELanguage] cla32

Description: verilog code for cla 32 bit adder
Platform: | Size: 29696 | Author: lee/asd | Hits:

[assembly language] 32-bit-cla-adder

Description: This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
Platform: | Size: 1024 | Author: hskim | Hits:

[Software Engineering] 11

Description: 32 bit cla, carry look aheader
Platform: | Size: 3072 | Author: david | Hits:

[DSP program] dsp28035cla

Description: CLA是一个32位浮点数学加速器，专为独立于TMS320C28x CPU内核工作而设计，以分担复杂的高速控制算法。-CLA is a 32-bit floating-point math accelerator, specially designed for independent of the TMS320C28x CPU kernel work, to share the complex high speed control algorithm.
Platform: | Size: 189440 | Author: 赵静 | Hits:

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