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[Embeded-SCM Develop] VHDLmipsPipeline

Description: 32 位MIP流水线CPU设计，5 stage，代码详细，包括ALU,存储器,寄存器等，是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
Platform: | Size: 561152 | Author: suborong | Hits:

[VHDL-FPGA-Verilog] alu32

Description: 32 bit ALU design using VHDL code for Xilinx ISE Foundation
Platform: | Size: 1024 | Author: Bruno Frankelli | Hits:

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