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[Windows Develop] Desktop

Description: It is 4 bit updown counter
Platform: | Size: 25600 | Author: Pratik | Hits:

[VHDL-FPGA-Verilog] ripple_carry_counter

Description: verilog 语言的简单的4为脉动进位计数器，附带仿真的激励块-verilog language into a simple 4-bit counter for the pulse, with the incentive simulation block
Platform: | Size: 398336 | Author: qirui | Hits:

[VHDL-FPGA-Verilog] 2

Description: 介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
Platform: | Size: 158720 | Author: xxx | Hits:

[VHDL-FPGA-Verilog] VHDLdigital

Description: 7段数码管译码器设计与实现 一．实验目的 1.　掌握7段数码管译码器的设计与实现 2.　掌握模块化的设计方法 二．实验内容 设计一个7段数码管译码器，带数码管的4位可逆计数器 [具体要求] 1. 7段数码管译码器 使用拨码开关SW3, SW2, SW1, SW0作为输入，SW3为高位，SW0为低位。 将输出的结果在HEX1，HEX0显示。当输入为‘0000’~‘1111’显示为00~15， 2. 带数码管的4位可逆计数器 将实验三的结果在数码管上显示。结合上次实验，将4位可逆计数器，数码管显示，分别作为两个子模块，实现在数码管上显示的4位可逆计数器。 -7 digital control design and implementation of the decoder 1. Purpose of the experiment 1. To master digital control decoder 7 Design and Implementation 2. Master modular design 2. Experimental content Design of a 7-segment digital tube decoder, with a digital 4-bit reversible counter tube [Specific requirements] 1.7 Duan digital control decoder Use DIP switch SW3, SW2, SW1, SW0 as input, SW3 is high, SW0 is low. The output of the HEX1, HEX0 display. When the input to 0000 ~ 1111 is displayed as 00 to 15, 2. With digital control of the 4-bit reversible counter The experimental results of the three digital tube display. Combined with the previous experiment, the 4-bit reversible counter, digital display, as the two sub-modules, respectively, to achieve in the digital tube display reversible 4-bit counter.
Platform: | Size: 89088 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] experiment4_play

Description: VHDL实验四，设计一个异步清零和同步时钟使能的4位加法计数器-VHDL Experiment 4, an asynchronous reset and synchronous design clock enable 4-bit adder counter
Platform: | Size: 195584 | Author: 童长威 | Hits:

[VHDL-FPGA-Verilog] lab_manual_tutorial

Description: 用赛灵思ISE9.2和Spartan-3E设计的四位计数器-4- Bit Counter with Xilinx ISE 9.2 and Spartan 3E
Platform: | Size: 319488 | Author: 飞飞三号 | Hits:

[VHDL-FPGA-Verilog] 4.ripple.counter

Description: 4位 ripple的寄存器计数器，代码和设计图-4 bit ripple counter code and layout
Platform: | Size: 19456 | Author: | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

[VHDL-FPGA-Verilog] counter_4bit_code

Description: vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares-vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares....
Platform: | Size: 40960 | Author: anmol | Hits:

[VHDL-FPGA-Verilog] COUNTER.ZIP

Description: 4 bit counter example for CHDL beginners
Platform: | Size: 1024 | Author: champan | Hits:

[VHDL-FPGA-Verilog] counter

Description: A 4 bit counter. In the testbench I combine three counters into one. Verilog codes with testbench.
Platform: | Size: 1024 | Author: cry | Hits:

[Software Engineering] counter

Description: 一、基础部分（70 ） 设计一个简易计算器，它具有下列运算功能： 1. 两个无符号的8位二进制数的相加； 2. 两个无符号的8位二进制数的相减； 3. 数值和运算符用4×4键盘输入，输入的值为十进制，其中A为“+”，B为“-”，C为“退格”E为“=”， 4. 数值用数码管以十进制形式显示，以加法为例，初始时显示全“0”，先输入被加数，输入时数字顺序是从左到右。例如，输入1、2、3应该在显示器上上显示“123”，在输入运算符，按下运算符键后，数码管显示全“0”，再输入加数，方法和前面一样，最后按下“=”，数码管显示运算结果 二、扩展部分（30 ） 在基础部分上增加乘法功能，实现两个无符号的4位二进制数的相乘，D为“*”（30 ）-First, the base portion (70 ) to design a simple calculator, it has the following expression: 1. Sum of two unsigned 8-bit binary number subtraction of two unsigned 8-bit binary number values ​ ​ and operators with 44 keyboard input, the input value is decimal, where A is the+ B for " -" C " backspace" E " =" Numerical digital tube In addition, for example, when the initial display of " 0" , the first input is addend input digital sequence is from left to right is displayed in decimal form. For example, enter 1, 2 and 3 on the display should be displayed on the " 123" digital display " 0" , the input operator, press the operator key, and then enter the addend, methods, and as before, and finally press under the " =" , digital display the result of the operation, expansion portion (30 ) increase in the base part multiplication function, the multiplication of two unsigned 4-bit binary number, D is the " *" (
Platform: | Size: 455680 | Author: 孟晓慧 | Hits:

[VHDL-FPGA-Verilog] 4-bit-Ripple-Carry-adder

Description: it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II.
Platform: | Size: 25600 | Author: Henal patel | Hits:

[VHDL-FPGA-Verilog] A-4-bit-variable-modulus-counter

Description: 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control of the cipher achieve synchronous mode 5, the die 8, a mold 10, the mold 12 and the task calls statement 5bit binary adder, a counter with synchronous clear and pause count function. Clocked at 50MHz, display frequency to 1 Hz.
Platform: | Size: 2048 | Author: 赵玉著 | Hits:

[LabView] asynchronous-4-bit-counter-down

Description: synchronous 4-bit counter by roling coming down
Platform: | Size: 13312 | Author: alisoltani | Hits:

[LabView] synchronous-4-bit-counter-up-on-10

Description: synchronous 4-bit counter up on 10
Platform: | Size: 14336 | Author: alisoltani | Hits:

[Embeded-SCM Develop] Reversible reversible 4 bit counter

Description: 利用AT89S51单片机的P1.0－P1.3接四个发光二极管L1－L4，用来指示当前计数的数据；用P1.4－P1.7作为预置数据的输入端，接四个拨动开关K1－K4，用P3.6/WR和P3.7/RD端口接两个轻触开关，用来作加计数和减计数开关。(The use of single-chip AT89S51 P1.0 P1.3 with four light emitting diode L1 L4, used to indicate the current count data; using P1.4 P1.7 as the input end of the preset data K1 K4 switch, four toggle, two touch switch with P3.6/WR and P3.7/RD port, used to count and count down switch.)
Platform: | Size: 51200 | Author: lastnight | Hits:

[Other] counter (2)

Description: This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
Platform: | Size: 1024 | Author: tariq | Hits:

[SCM] Reversible reversible 4 bit counter

Description: 可预制数的4位可逆计数器设计，protues平台 51单片机 全套工程文件：C源码、电路图及文明文档等(4 digit reversible counter design can be prefabricated, Protues platform, 51 single-chip full set of engineering documents: C source code, circuit diagrams and civilized documents)
Platform: | Size: 78848 | Author: zhaoren | Hits:

[Embeded-SCM Develop] 4位BCD计数器

Description: 用Verilog语言编程实现4位BCD计数器的功能(Write the programm with Verilog language to implement the function of 4 - bit BCD counter.)
Platform: | Size: 25600 | Author: limaozi | Hits:
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