Description: 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间；
因为各状态持续时间不一致，所以上述计数器应置入不同的预置数；
倒计时计数值输出至二个数码管显示；
程序共设置4个进程：
① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号；
② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code countdown counter (count pulse 1HZ), used to record the duration of each state because the duration of each state are inconsistent, so these counters should be placed in several different presets countdown of numerical output to two digital display procedures were set up four processes: ① process P1, P2 and P3 form two functions with a preset number of decimal counters, of which P1 and P3, respectively, for months, and 10-bit counters, P2 to generate a 10-bit The binary signal ② P4 is the status register, control the state of the conversion, and six output control signals of traffic lights. Platform: |
Size: 1024 |
Author:kid |
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Description: Ripple carry counter with 4 bit resolution implemented in behavioral VHDL. attaches as well is a jpg with the logic gates bock diagram. this is an asinchronous design. Platform: |
Size: 12288 |
Author:avi |
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Description: 此實驗中我們將量 測人的反應時間，由於人的反應時間遠比起內建CLOCK的週
期長的多，因此要對CLOCK做除頻的動作方可適用，並方便 於計數 器的計算與
七段顯示器的呈現。實驗內容為，當看到LED亮 起時，立 即做出反應將計數 器停
下，並顯示出當時計數 器之時間。計數 器以兩 位數 BCD counter來 實現並將結果
顯示於七段顯示器上。-Volume in this experiment we will test people' s reaction time, because people' s reaction time is far longer than the built-in multi-CLOCK cycle, and therefore the frequency of CLOCK to do except be applicable to the action, and facilitate in the total number of device Computing and seven-segment display rendering. Test content, when you see LED Leung from time to time, to respond immediately to stop the total number of devices and demonstrate the total number of devices was the time. Total number of devices with two-bit number of BCD counter future to achieve the results shown in the seven-segment display. Platform: |
Size: 141312 |
Author:徐小華 |
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Description: 7段数码管译码器设计与实现
一．实验目的
1. 掌握7段数码管译码器的设计与实现
2. 掌握模块化的设计方法
二．实验内容
设计一个7段数码管译码器，带数码管的4位可逆计数器
[具体要求]
1. 7段数码管译码器
使用拨码开关SW3, SW2, SW1, SW0作为输入，SW3为高位，SW0为低位。
将输出的结果在HEX1，HEX0显示。当输入为‘0000’~‘1111’显示为00~15，
2. 带数码管的4位可逆计数器
将实验三的结果在数码管上显示。结合上次实验，将4位可逆计数器，数码管显示，分别作为两个子模块，实现在数码管上显示的4位可逆计数器。
-7 digital control design and implementation of the decoder
1. Purpose of the experiment
1. To master digital control decoder 7 Design and Implementation
2. Master modular design
2. Experimental content
Design of a 7-segment digital tube decoder, with a digital 4-bit reversible counter tube
[Specific requirements]
1.7 Duan digital control decoder
Use DIP switch SW3, SW2, SW1, SW0 as input, SW3 is high, SW0 is low.
The output of the HEX1, HEX0 display. When the input to 0000 ~ 1111 is displayed as 00 to 15,
2. With digital control of the 4-bit reversible counter
The experimental results of the three digital tube display. Combined with the previous experiment, the 4-bit reversible counter, digital display, as the two sub-modules, respectively, to achieve in the digital tube display reversible 4-bit counter. Platform: |
Size: 89088 |
Author:爱好 |
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Description: 八音自动播放电子琴设计 vhdl源码，文件内有具体注释
[VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9-
-Octave electronic keyboard play automatically design vhdl source, document specific comments [VHDL-XILINX-EXAMPLE26.rar]- [VHDL design of 26 cases of classic]- in the xilinx chip debugging through- [01- 1 adder ] [02- 2 S 1 MUX] [03- 8-bit hardware adder] [04- 7-segment digital display decoder] [05- 8 bit string into and out of register] [6--8 bit string into a register] [7- internal three-state bus] [8- with clear and clock enable synchronous 4-bit adder counter] [9- Platform: |
Size: 231424 |
Author:杨领超 |
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Description: 四位10进制VHDL频率计设计说明
四位频率计的结构包括一个测频率控制信号发生器、四个十进制计数器和一个十六位锁存器（本例中所测频率超过测频范围时有警示灯）。-Four 10-digit frequency counter VHDL design description of the structure of the four frequency meter includes a measuring frequency control signal generator, four decimal counter and a sixteen bit latch (in this case the measured frequency over a frequency measurement range warning lights). Platform: |
Size: 54272 |
Author:韦昊斯 |
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Description: vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares-vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares.... Platform: |
Size: 40960 |
Author:anmol |
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Description: it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II. Platform: |
Size: 25600 |
Author:Henal patel |
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Description: Write VHDL specifications for an eight bit twisted ring counter based on each of the
designs in the previous problem. Look at the synthesis report generated by the design tools
(use the Spartan 2 xc2s15-cs144-6 part for this). How many flip flops are required for each of
the designs? How many LUTs of all types? What is the maximum estimated clock
frequency? Platform: |
Size: 45056 |
Author:john |
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Description: 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following
features:
(1) The same ports are used for signals to be inputted and outputted. The ports are
bi-directionally buffered (three-state).
(2) The counter is with an asynchronous reset that assigns a specific initial value
for counting.
(3) The counter is with a synchronous data load control input for a new value of
counting and an enable control input for allowing the up and down counting.
The load control input has a priority over the enable control input. This
implies that when the load operation is in process the counter operation is
prohibited.
(4) Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER,
may be used) Platform: |
Size: 1014784 |
Author:名之联 |
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