Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - 7-segment FPGA

Search list

[VHDL-FPGA-Verilog] hourse_race_light(7seg)

Description: 这是我用Xilnx公司的sparten3 FPGA开发板上，用集成开发环境ISE设计制作的一个跑马灯程序，就如同一个小型的霓虹灯。供大家参考。-This is the company I used Xilnx the sparten3 FPGA development board. use integrated development environment ISE design of a Bomadeng procedures, it is like a small neon lights. For your reference.
Platform: | Size: 7168 | Author: 汪莉莉 | Hits:

[VHDL-FPGA-Verilog] rafal2

Description: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Platform: | Size: 941056 | Author: nukom | Hits:

[Technology Management] segment

Description: 7 segment display using verilog interfacing fpga and 7 segment display
Platform: | Size: 311296 | Author: kripa | Hits:

[VHDL-FPGA-Verilog] Mars-EP1C6-F_code2

Description: 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD, I2C bus, serial communication, DIP switch.
Platform: | Size: 4633600 | Author: sunxh092 | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C3_S_Core_V2.0

Description: 此包中为Mars_EP1C3_S_Core_V2.0 FPGA学习板中的接口实验代码.共包括10个实验源代码:7段数码管,i2c,KEYSCAN,MCU,PS2,UART,VGA，蜂鸣器，跑马灯和拨码开关. -This learning package for Mars_EP1C3_S_Core_V2.0 FPGA board interface test code. A total of 10 experiments, including source code: 7 segment digital tube, i2c, KEYSCAN, MCU, PS2, UART, VGA, buzzer, marquees and dial switch.
Platform: | Size: 2184192 | Author: wzh | Hits:

[VHDL-FPGA-Verilog] success

Description: 各种FPGA初级入门程序（已调试通过），包括计数器、流水灯、7段数码管显示以及PS2键盘接口驱动，采用VHDL语言编写，适合初学者参考-Various FPGA primary entry procedures (already debugged), including the counter, water light, 7 segment LED display and PS2 keyboard interface driver, using VHDL language, suitable for beginners reference
Platform: | Size: 1449984 | Author: 王玉强 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: FPGA驱动LED静态显示代码，7段显示码，可以增加显示管的数量完成一些简单的设备-FPGA-driven LED static display code, 7-segment display code, can increase the number of display tubes to complete some simple equipment
Platform: | Size: 3072 | Author: 朱林 | Hits:

[VHDL-FPGA-Verilog] LED_7seg

Description: FPGA的7段数码管程序，用verilog编写，很好的程序，不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
Platform: | Size: 220160 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] Stopwatch

Description: Stop-watch for FPGA on 7 segment display
Platform: | Size: 6144 | Author: Aida | Hits:

[VHDL-FPGA-Verilog] shumaguan

Description: 基于FPGA的7段数码管从0到F循环显示代码-FPGA-based 7-segment LED display from 0 to F loop code
Platform: | Size: 52224 | Author: 宋小柒 | Hits:

[VHDL-FPGA-Verilog] ISE_lab5

Description: 使用VHDL 语言编写7 段数码管显示程序， 掌握数码管的驱动方法。使用USB 电缆或并口下载线下载逻辑电路到FPGA，并 调试电路使其正常工作。-Using the VHDL language 7-segment display program, for digital control of the driving method. Using the USB cable or parallel port download cable to download logic to FPGA, and debug the circuit to work properly.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] Final

Description: 乘法器,模拟两个0-99的数相乘，将结果显示在7段数码管上，可FPGA平台烧制~-Multiplier, two 0-99 multiplying the number of analog, the results displayed in the 7-segment digital tube, may FPGA platform firing ~
Platform: | Size: 540672 | Author: LastSun | Hits:

[VHDL-FPGA-Verilog] LED_0000_9999

Description: 使用FPGA编写代码，可以实现了7段数码管动态显示0000-9999功能。-Using FPGA to write code, you can achieve a 7-segment digital tube dynamic display 0000-9999 function.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] Alu-with-seven-segmetn-output

Description: This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be easily ported to other fpga s.
Platform: | Size: 8192 | Author: hatsjoe | Hits:

[VHDL-FPGA-Verilog] qi-duan-yi-ma-qi

Description: 七段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用译码程序在FPGA\CPLD中来实现。本实验作为7段译码器，输出信号LED7S的7位分别是g、f、e、d、c、b、a，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别为1、1、0、1、1、1、0、1。接有高电平段发亮，于是数码管显示“5”。-Seven-Segment is a pure combinational circuit, usually small-scale special IC, such as 74 or 4000 Series devices only for decimal BCD decoding, digital systems, however data processing and operations are binary, so the output expression hexadecimal, in order to meet the decoding of the hex number display, the most convenient way is to use a decoding program to implement in the FPGA \ CPLD. In this study, as a 7-segment decoder, the output signal LED7S 7 g, f, e, d, c, b, a, high in the left, low on the right. For example, when LED7S output for " 1101101" digital tube 7 paragraph g, f, e, d, c, b, a, respectively 1,1,0,1,1,1,0,1. Access the high level segment shiny, so the digital display " 5" .
Platform: | Size: 3072 | Author: xuling | Hits:

[VHDL-FPGA-Verilog] seg7_disp

Description: Spartan xc3S400 FPGA 7-Segment VHDL Program
Platform: | Size: 358400 | Author: ibrahim | Hits:

[assembly language] UART_RS232(verilog)

Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Platform: | Size: 600064 | Author: 饕餮小宇 | Hits:

[VHDL-FPGA-Verilog] TimingTheWorld_Decimal

Description: 计时,最短时间为100Hz，BASYS2 board,FPGA 可以在7-Segment上显示时间。-Timing the world
Platform: | Size: 287744 | Author: Mao Yimeng | Hits:

[VHDL-FPGA-Verilog] Keyb27Seg

Description: VHDL codes for Multiplexed 7 segment LED, verified for Spartan3E (Basys2) FPGA board. This is part of Digital System Design course at Fasilkom UI.
Platform: | Size: 7168 | Author: santo | Hits:

[Embeded Linux] Cyclone V HPP demonstration

Description: C source code that exemplifies the use of the Cyclone V FPGA on a development board. Function exemplified: - the communication between the HPP and the FPGA - using the audio output - using LEDs - using switches - using 7 segment display
Platform: | Size: 12241 | Author: serby2000 | Hits:
« 12 »

CodeBus www.codebus.net