Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - 754 add

Search list

[VHDL-FPGA-Verilog] add(FLP)

Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Platform: | Size: 10240 | Author: TTJ | Hits:

[Other] IEEE_854.pdf

Description: 浮点计算的补充标准，补充了ieee-754标准-Supplementary standard floating-point calculations, add the ieee-754 standard
Platform: | Size: 108544 | Author: 1 | Hits:

[VHDL-FPGA-Verilog] CORDIC_FPGA

Description: 摘要：本文在传统CORDIC算法的基础之上，通过增加迭代次数，对参数进行了优化筛选， 提高了运算精度，使设计出的软核能够在精度要求较高的场合中运行，如实时语音、图 像信号处理、滤波技术等。输出数据经过IEEE-754标准化处理，能够直接兼容大多数处 理器，扩展了其应用范围。最终在Altera公司NiosⅡ处理器中通过增加自定义指令的方 式完成了硬件实现。 关键字：CORDIC ,自定义指令, IEEE-754标准化处理。-Abstract: In this paper, based on the traditional CORDIC algorithm, by increasing the number of iterations, selection of parameters were optimized to improve the computing precision, the design of the soft-core to the occasion in the high precision in the running, such as real-time voice , image signal processing, filtering technology. IEEE-754 output data after standardization, can be directly compatible with most processors, expanded its scope of application. Altera, Nios Ⅱ ultimately by the processor the way to add custom instructions to complete the hardware. Keywords: CORDIC, custom instruction, IEEE-754 standard treatment.
Platform: | Size: 228352 | Author: daisywmc | Hits:

[VHDL-FPGA-Verilog] Float_point

Description: 浮点数加/减法器的设计 规格化的浮点数运算器 IEEE标准754 单精度-Floating-point add/subtract device design normalized floating-point arithmetic unit single-precision IEEE Standard 754
Platform: | Size: 5120 | Author: tong | Hits:

[VHDL-FPGA-Verilog] Handbook-of-Floating-Point-Arithmetic---Birkhause

Description: Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Standard, New IEEE 754-2008 Standard)-Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Standard, New IEEE 754-2008 Standard)
Platform: | Size: 5574656 | Author: ricvadim | Hits:

[VHDL-FPGA-Verilog] FPU

Description: 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
Platform: | Size: 115712 | Author: gingercorn | Hits:

[Linux-Unix] s_significand

Description: for exercising the fraction-part(F) IEEE 754-1985 test vector.NDK r8d: Add android_setCpu().
Platform: | Size: 12288 | Author: gahieyei | Hits:

CodeBus www.codebus.net