Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: add(FLP) Download
 Description: A 32-bit floating-point adder can be both within the IEEE 754 format to add value
 Downloaders recently: [More information of uploader terry731130]
File list (Check if you may need any files):
add(FLP)
........\architecture.txt
........\fpadd_32.vhd
........\fpadd_32tb.v
........\fpadd_normalize.vhd
........\fpalign.vhd
........\fpinvert.vhd
........\fplzc.vhd
........\fpnormalize.vhd
........\fpround.vhd
........\fpselcomplement.vhd
........\fpswap.vhd
........\packfp.vhd
........\transcript
........\unpackfp.vhd
........\vish_stacktrace.vstf
    

CodeBus www.codebus.net