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[ADO-ODBC] 8bit_multi_pipeline

Description: 8 bit multiplier with pipeline design, mainly for studying and learning purpose
Platform: | Size: 1024 | Author: q | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[DSP program] MulPar

Description: 八位乘法器VHDL语言实现。使用的工具的ISE7.1，实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
Platform: | Size: 2048 | Author: 周东永 | Hits:

[Other] 8

Description: 移位相加8位硬件乘法器电路设计 乘法器是数字系统中的基本逻辑器件，在很多应用中都会出现如各种滤波器的设计、矩阵的运算等。本实验设计一个通用的8位乘法器。-Shift combined 8-bit hardware multiplier multiplier circuit design is a digital system in the basic logic devices, in many applications will emerge, and such a variety of filter design, such as matrix calculations. The experimental design of a generic 8-bit multiplier.
Platform: | Size: 5120 | Author: jun | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[Other] 8-bit_multiplier

Description: 用ASM原理做二進位8-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
Platform: | Size: 1024 | Author: 沉默劍士 | Hits:

[VHDL-FPGA-Verilog] 8-bit-Multiplier

Description: 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
Platform: | Size: 1024 | Author: 杨波 | Hits:

[Other] mul

Description: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door
Platform: | Size: 1024 | Author: 肖毅 | Hits:

[Other] MUL

Description: 8-bit modified Booth s algorithm multiplier
Platform: | Size: 80896 | Author: calvin | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplication through the principle of each shift to achieve, from the beginning of the lowest multiplicand, if 1, then left after the multiplier and the sum of the last if for 0, left after zero-sum in full, until the highest bit multiplicand.
Platform: | Size: 103424 | Author: lsp | Hits:

[Windows Develop] mult4x4_1

Description: There are 4 bit by 4 bit multiplier to give 8 bit product
Platform: | Size: 1024 | Author: abbc | Hits:

[Windows Develop] baughWooleyMultiplier

Description: gate level implementation of 8*8 Signed baugh wooley multiplier!
Platform: | Size: 1024 | Author: Majid | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: verilog program for 8-bit multiplier
Platform: | Size: 216064 | Author: Arjun | Hits:

[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl)

Description: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Platform: | Size: 967680 | Author: jlz | Hits:

[VHDL-FPGA-Verilog] dsa_code

Description: Verilog code for synthesis of 8-bit booth multiplier
Platform: | Size: 4096 | Author: tanish | Hits:

[Embeded-SCM Develop] boothmultiplier

Description: booth算法描述， 8乘8位带符号校验扩展位乘法器-booth algorithm description, 8 x 8 bit multiplier with symbol check extension
Platform: | Size: 1024 | Author: 智航 | Hits:

[VHDL-FPGA-Verilog] 8by8multiplier

Description: Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..
Platform: | Size: 49152 | Author: VINOD | Hits:

[VHDL-FPGA-Verilog] VHDL-based-8-bit-multiplier

Description: 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
Platform: | Size: 3072 | Author: 周益驰 | Hits:

[VHDL-FPGA-Verilog] 8-bit-Multiplier

Description: Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the third step, s2, the product is transferred to the output register y.
Platform: | Size: 193536 | Author: hooman hematkhah | Hits:
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