Search - 8b10b vhdl

[Other resource] 8b10b_Encoder

Description: 应用VHDL设计的8b10b 编码器，对串行数据的高速传输有用。-application VHDL design 8b10b encoding device to the high-speed serial data transmission useful.
Platform: | Size: 78239 | Author: taitango | Hits:

[VHDL-FPGA-Verilog] 8b10b_Encoder

Description: 应用VHDL设计的8b10b 编码器，对串行数据的高速传输有用。-application VHDL design 8b10b encoding device to the high-speed serial data transmission useful.
Platform: | Size: 77824 | Author: | Hits:

[VHDL-FPGA-Verilog] 8b10b_Decoder

Description: 应用VHDL设计的8b10b解码器源文件，实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
Platform: | Size: 18432 | Author: | Hits:

[VHDL-FPGA-Verilog] E016_X-HDL3.2.52

Description: VHDL和Verilog代码互转工具,对EDA工程人员会有很大的帮助.-VHDL and Verilog code referrals tools, EDA staff to be very helpful.
Platform: | Size: 3962880 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 72704 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec

Description: VHDL写的8B10B编码解码器的实现，在Xilinx平台通过验证。-Written in VHDL coding 8B10B decoder realize, in the Xilinx platform validated.
Platform: | Size: 70656 | Author: 张开文 | Hits:

[Other] 8b10B

Description: 8b10b编解码器，常用于camera link,1394等高速信号传输-8B10B CODECs, commonly used in the camera link, 1394, such as high-speed signal transmission
Platform: | Size: 69632 | Author: 张家大少 | Hits:

[Com Port] 8b10b_pdf

Description: 8b10b编解码设计的pdf文章,用于现代千兆网通信,快速串行通信.-.pdf paper
Platform: | Size: 1703936 | Author: hanhaili | Hits:

[Crack Hack] 8b10b

Description: 8b_10b encoder/decoder
Platform: | Size: 69632 | Author: dinesh | Hits:

[VHDL-FPGA-Verilog] 8b10b

Description: 如题,原始8B10B编码，仿真通过。真麻烦，要说那么多废话-as title
Platform: | Size: 182272 | Author: luojinc | Hits:

[assembly language] Giga8b10bv10

Description: altera发布的开源8b10b源代码，vhdl语言描述-altera released the source code open source 8b10b, vhdl language description
Platform: | Size: 24576 | Author: 颜回中 | Hits:

[VHDL-FPGA-Verilog] 8B10B

Description: 基于VHDL的双校验位8B10B编码系统的设计，对于学习VHDL语言有一定的帮助-VHDL-based dual-parity bit 8B10B coding system for learning VHDL, there is some help
Platform: | Size: 396288 | Author: 李博 | Hits:

[VHDL-FPGA-Verilog] Altera_IP_verilog

Description: Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
Platform: | Size: 395264 | Author: Gorce | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec

Description: 8b10b编码模块的设计，用vhdl语言仿真-8b10b coding module design, simulation using vhdl language
Platform: | Size: 73728 | Author: 杨芳名 | Hits:

[VHDL-FPGA-Verilog] 8b10b_dec

Description: vhdl语言编写，8b10b解码器模块设计-vhdl language, 8b10b Decoder Module
Platform: | Size: 2048 | Author: 何沐 | Hits:

[VHDL-FPGA-Verilog] 8b10b_enc

Description: vhdl语言编写，8b10b解码器模块设计-vhdl language, 8b10b Decoder Module
Platform: | Size: 3072 | Author: 何沐 | Hits:

[VHDL-FPGA-Verilog] altera_lib

Description: 实现基于VHDL语言的8b10b编解码器，在altera平台得到验证。-8b10b VHDL language-based codec, in altera platform to be validated.
Platform: | Size: 17408 | Author: 李嘉洁 | Hits:

[VHDL-FPGA-Verilog] 8b10b

Description: 8b/10b编解码模块，VHDL语言设计，经过编译，里面有测试平台以及文档。不可错过哦！-The 8b/10b encoding and decoding modules, VHDL language design, compilation, there are test platforms, and documentation. Not miss it!
Platform: | Size: 69632 | Author: 西门吹雪 | Hits:

[Windows Develop] b8b__10bbi

Description: vhdl开发，8b—10b 编解码器设计Encoder: 8bb/10b Encoder (file: 8b10b -vhdl development, 8b-10b codec design Encoder: 8bb/10b Encoder (file: 8b10b
Platform: | Size: 72704 | Author: nu | Hits:

[Communication-Mobile] 8b10bvhd

Description: 利用VHDL语言为工具，进行8b10b编解码的编写(The use of VHDL language as a tool for the preparation of 8B10B codec)
Platform: | Size: 69632 | Author: 臭猴子 | Hits:

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[Other resource] 8b10b_Encoder

[VHDL-FPGA-Verilog] 8b10b_Encoder

[VHDL-FPGA-Verilog] 8b10b_Decoder

[VHDL-FPGA-Verilog] E016_X-HDL3.2.52

[VHDL-FPGA-Verilog] 8b_10b

[VHDL-FPGA-Verilog] 8b10b_encdec

[Other] 8b10B

[Com Port] 8b10b_pdf

[Crack Hack] 8b10b

[VHDL-FPGA-Verilog] 8b10b

[assembly language] Giga8b10bv10

[VHDL-FPGA-Verilog] 8B10B

[VHDL-FPGA-Verilog] Altera_IP_verilog

[VHDL-FPGA-Verilog] 8b10b_encdec

[VHDL-FPGA-Verilog] 8b10b_dec

[VHDL-FPGA-Verilog] 8b10b_enc

[VHDL-FPGA-Verilog] altera_lib

[VHDL-FPGA-Verilog] 8b10b

[Windows Develop] b8b__10bbi

[Communication-Mobile] 8b10bvhd

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