Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - ACEX1K

Search list

[File Operate] 147497_ALTERA_ACEX1K

Description: 147497_ALTERA_ACEX1K.pdf介绍alter acex1k系列芯片
Platform: | Size: 380650 | Author: tomtan | Hits:

[File Format] 147497_ALTERA_ACEX1K

Description: 147497_ALTERA_ACEX1K.pdf介绍alter acex1k系列芯片-147497_ALTERA_ACEX1K.pdf introduce alter acex1k series chip
Platform: | Size: 379904 | Author: tomtan | Hits:

[VHDL-FPGA-Verilog] music

Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Platform: | Size: 8192 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] colorful_signal

Description: 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 由系统提供的时钟源引入扫描信号，根据VGA彩色显示器的工作原理，设计出各种颜色编码和行场扫描信号。将并口线从计算机并口与CPLD/FPGA适配板连接好，然后将VGA接口与彩色显示器连接好，彩条信号就可以在显示器中产生，通过按键可以改变产生彩条的方式，共六种彩条信号，两种横彩条，两种竖彩条，两种棋盘格。本实验运用层次化设计出VGA彩条信号发生器，由行场信号模块模块和彩条信号发生模块构成，彩条信号发生器的顶层原理图如图10.7 所示. -err
Platform: | Size: 7168 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] FPGA2SRAM

Description: verilog code that can implemented on ACEX1k FPGA for a SRAM-verilog code that can implemented on ACEX1k FPGA for a SRAM
Platform: | Size: 221184 | Author: z | Hits:

[VHDL-FPGA-Verilog] freq

Description: a verilog hdl code that contains script for dividing frequencies in ACEX1K Altera FPGA Board.
Platform: | Size: 29696 | Author: z | Hits:

[Embeded-SCM Develop] DigitalStopwatch

Description: 本数字秒表采用ALTERA公司ACEX1K系列的EP1K100QC208-3芯片为核心。数字秒表实现的功能：按开始开关启动秒表并开始计时，实现了从0.01秒到59分59.99秒的计时，若期间由于某种需要，按下暂停开关（开始开关），当事情解决，重新按下开始开关，使其从暂停状态恢复到工作状态。，当下一次计时时，按下清零开关，对其进行清零操作。-The digital stopwatch using ALTERA company ACEX1K series EP1K100QC208-3 chip as the core. Implemented digital stopwatch function: Press start switch starts the stopwatch and begin timing, achieved 59 minutes from 0.01 seconds to 59.99 seconds in the timing, duration, if for some need, press the pause switch (start switch), when the matter resolved, re-press begun to switch to resume from suspend state to a working state. , Next time time, press the reset switch to clear their operations.
Platform: | Size: 17408 | Author: sunnan | Hits:

[Driver Develop] v1.7.4-RC

Description: 超声波流量计的部分设计程序，此部分为控制芯片ACEX1K系列的EP1K50QC208-3中的代码，采用的是VHDL语言，里面包括LCD12864的读写代码、流量的处理等-Ultrasonic flowmeter in which the design process, this part of the control chip ACEX1K series EP1K50QC208-3 in the code, using the VHDL language, which includes LCD12864 read and write code, traffic handling
Platform: | Size: 2397184 | Author: daniel | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 实现跑表功能精确度为0.01秒。（使用ACEX1K系列EP1K30TC144-3芯片）-Stopwatch function to achieve an accuracy of 0.01 seconds. (Using ACEX1K series EP1K30TC144-3 chip)
Platform: | Size: 189440 | Author: Haifengqingfu | Hits:

[Software Engineering] Altera-ACEX1K-datasheet

Description: ALTERA ACEX1K Datasheet
Platform: | Size: 536576 | Author: VVAP | Hits:

[VHDL-FPGA-Verilog] finaldesign_watch

Description: 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for the development, the use of the VHDL language, from 0.01 seconds to 59 minutes 59 seconds 59 design.
Platform: | Size: 985088 | Author: huyanting | Hits:

CodeBus www.codebus.net