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[VHDL-FPGA-Verilogviterbi

Description: 硬判决viterbi译码的硬件实现,通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Platform: | Size: 92160 | Author: Fengxiaodong | Hits:

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