Welcome![Sign In][Sign Up]
Location:
Search - AES CODE VHDL

Search list

[Crack Hackaes_encryption

Description: aes加密算法的VHDL代码实现,在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[VHDL-FPGA-VerilogCoreAES128

Description: Full AES Simulation Code
Platform: | Size: 1339392 | Author: esl | Hits:

[Crack Hackmini_aes_latest[1].tar

Description: AES 加解密 代码, 有文档说明,testbench-AES encoding decoding source code in HDL
Platform: | Size: 233472 | Author: wangbin | Hits:

[AlgorithmAES

Description: This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
Platform: | Size: 10240 | Author: Krupesh | Hits:

[source in ebook63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块,用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[Crack Hacksystemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[Software Engineeringfifo_template

Description: aes code with fifo control to memory
Platform: | Size: 9216 | Author: allen | Hits:

[matlabaes

Description: Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
Platform: | Size: 8192 | Author: allen | Hits:

[Crack Hackaes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[VHDL-FPGA-Verilogaescore

Description: 基于FPGA的AES算法实现的VERILOG源代码,对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Platform: | Size: 195584 | Author: 李华 | Hits:

[Program doccunzip

Description: AES CODE FOR DECRYPTION
Platform: | Size: 12288 | Author: sruthi | Hits:

[Program docRijndael

Description: AES USING PICOBLAZE CODE
Platform: | Size: 17408 | Author: sruthi | Hits:

[VHDL-FPGA-VerilogAES!

Description: AES algorithm very good code tested in xilinx ise tool
Platform: | Size: 9216 | Author: hr | Hits:

[VHDL-FPGA-Verilogaes

Description: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Platform: | Size: 2973696 | Author: cong | Hits:

[VHDL-FPGA-Verilogsbox

Description: verilog code for s-box generation for AES algorith
Platform: | Size: 1024 | Author: clock | Hits:

[VHDL-FPGA-Verilog09912007AEScoremodules

Description: aes description architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
Platform: | Size: 6144 | Author: tarang | Hits:

[VHDL-FPGA-Verilogaes-vhdl

Description: this file contains vhdl code for aes
Platform: | Size: 119808 | Author: baby | Hits:

[File FormatAES-FPGA

Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现,语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Platform: | Size: 191488 | Author: Eric | Hits:

[Crack Hackaes_thesis_v1.0

Description: aes code in verilog vhdl language which is very useful.
Platform: | Size: 385024 | Author: sur22 | Hits:

[VHDL-FPGA-Verilogaes-master

Description: aes master by vhdl code and decode
Platform: | Size: 68608 | Author: Nguyen Nam | Hits:
« 12 »

CodeBus www.codebus.net