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Description: aes加密算法的VHDL代码实现,在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
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Size: 6144 |
Author: stym_001 |
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Description: Full AES Simulation Code
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Size: 1339392 |
Author: esl |
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Description: AES 加解密 代码, 有文档说明,testbench-AES encoding decoding source code in HDL
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Size: 233472 |
Author: wangbin |
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Description: This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
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Size: 10240 |
Author: Krupesh |
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Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块,用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
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Size: 2048 |
Author: jiang |
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Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
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Size: 83968 |
Author: lxc |
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Description: aes code with fifo control to memory
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Size: 9216 |
Author: allen |
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Description: Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
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Size: 8192 |
Author: allen |
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Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
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Size: 386048 |
Author: 蕭嵎之 |
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Description: 基于FPGA的AES算法实现的VERILOG源代码,对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
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Size: 195584 |
Author: 李华 |
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Description: AES CODE FOR DECRYPTION
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Size: 12288 |
Author: sruthi |
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Description: AES USING PICOBLAZE CODE
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Size: 17408 |
Author: sruthi |
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Description: AES algorithm very good code tested in xilinx ise tool
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Size: 9216 |
Author: hr |
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Description: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
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Size: 2973696 |
Author: cong |
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Description: verilog code for s-box generation for AES algorith
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Size: 1024 |
Author: clock |
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Description: aes description architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
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Size: 6144 |
Author: tarang |
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Description: this file contains vhdl code for aes
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Size: 119808 |
Author: baby |
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Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现,语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by
using different architecture of mixcolumn. We then review this research investigates the AES algorithm in
FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera
Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of
transformations of both Encryptions and decryption are simulated using an iterative design approach in
order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
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Size: 191488 |
Author: Eric |
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Description: aes code in verilog vhdl language which is very useful.
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Size: 385024 |
Author: sur22
|
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Description: aes master by vhdl code and decode
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Size: 68608 |
Author: Nguyen Nam |
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