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Title: aes Download
 Description: aes encryption decryption algorithm source code and test source code and simulation results map
 Downloaders recently: [More information of uploader wwoshimaojcl]
 To Search: AES AES VHDL VHDL code of AES aes algorithm vhdl code AES VHDL VHDL code for encryption and decryption
  • [ata.tar] - The use of two types of Verilog and VHDL
  • [verilog] - For the expansion of key aes128 encrypti
  • [53lift] - 5,3 wavelet few on FPGA hardware impleme
  • [aes] - aes encryption algorithm, after FPGA val
  • [aes_cipher_top] - 密钥扩展模块的接口如图4.4。clk为系统时钟，kld为输入的加载信号，key为
  • [gsrd_7_1_2] - Gbit-class xilinx passage under the refe
  • [aes128] - AES to achieve efficiency, such as area,
  • [aes_inv_cipher_top] - aes ip core, 128 bits
  • [aips7108.tar] - Simulation Model SATA SATA SATA simulati
  • [AES_test] - verilog AES ACTEL FPGA
File list (Check if you may need any files): 
11.2\aes.cr.mti
....\aes.mpf
....\aes.v
....\byte_mixcolum.v
....\keysched.v
....\mixcolum.v
....\sbox.v
....\subbytes.v
....\test_bench_top.v
....\timescale.v
....\transcript
....\vsim.wlf
....\wb_aescontroller.v
....\word_mixcolum.v
....\...k\_info
....\....\word_mixcolum\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\.b_aes_controller\_primary.dat
....\....\.................\_primary.vhd
....\....\.................\verilog.asm
....\....\test_bench_top\_primary.dat
....\....\..............\_primary.vhd
....\....\..............\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\subbytes\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\.box\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\mixcolum\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\keysched\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\byte_mixcolum\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\aes\_primary.dat
....\....\...\_primary.vhd
....\....\...\verilog.asm
....\.ave\Thumbs.db
....\....\aes.bmp
....\....\keysched.bmp
....\....\mixcolum.bmp
....\....\sbox.bmp
....\....\subbytes.bmp
....\....\test_bench_top.bmp
....\chart\Thumbs.db
....\.....\图11-25.bmp
....\.....\图11-28.bmp
....\.....\图11-31.bmp
....\.....\图11-32.bmp
....\.....\图11-33.bmp
....\.....\图11-35.bmp
....\.....\图11-36.bmp
....\.....\图11-38.bmp
....\.....\图11-39.bmp
....\.....\图11-42.bmp
....\.....\图11-43.bmp
....\work\word_mixcolum
....\....\wb_aes_controller
....\....\test_bench_top
....\....\test
....\....\subbytes
....\....\sbox
....\....\mixcolum
....\....\keysched
....\....\byte_mixcolum
....\....\aes
....\work
....\wave
....\chart
11.2

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