Search - AES code in verilog

Search - AES code in verilog - List

[Crack Hack] aes_core DL : 0: Verilog实现AES加密算法密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Update : 2025-02-17 Size : 78kb Publisher : yuansuchun
[source in ebook] 63535312DCTofJPEG DL : 0: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Update : 2025-02-17 Size : 2kb Publisher : jiang
[Crack Hack] systemcaes_latest.tar DL : 0: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Update : 2025-02-17 Size : 82kb Publisher : lxc
[Crack Hack] aes_thesis_v1.0 DL : 0: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Update : 2025-02-17 Size : 377kb Publisher : 蕭嵎之
[VHDL-FPGA-Verilog] aescore DL : 0: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Update : 2025-02-17 Size : 191kb Publisher : 李华
[VHDL-FPGA-Verilog] sbox DL : 0: verilog code for s-box generation for AES algorith
Update : 2025-02-17 Size : 1kb Publisher : clock
[CA auth] aes-module DL : 0: its a aes source code in verilog
Update : 2025-02-17 Size : 11kb Publisher : p
[Crack Hack] AES-based-on-FPGA-jiami DL : 0: 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
Update : 2025-02-17 Size : 14.25mb Publisher : 庄德坤
[VHDL-FPGA-Verilog] aes DL : 0: contains AES doc with code in Verilog
Update : 2025-02-17 Size : 939kb Publisher : sravs
[Crack Hack] aes_thesis_v1.0 DL : 0: aes code in verilog vhdl language which is very useful.
Update : 2025-02-17 Size : 376kb Publisher : sur22