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[Crack Hack] 高级加密算法

Description: AES加密和解密源码！-AES encryption and decryption source!
Platform: | Size: 101376 | Author: 古月 | Hits:

[Crack Hack] aes_encrypt

Description: AES加密软件，用于加密当前文本框中的内容。使用的是美国国家标准（也被ISO所采纳）最新加密算法AES。-AES encryption software, encryption for the current contents of the text box. The use of the American National Standards (also adopted by the ISO) the latest encryption algorithm AES.
Platform: | Size: 216064 | Author: | Hits:

[Crack Hack] aes_8bit

Description: VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits-VHDL realize 128bitAES encryption algorithm LOW AREA realize cost-saving DATA FLOW for 8 bits
Platform: | Size: 19456 | Author: ZHUOHUI LI | Hits:

[Crack Hack] aes_encryption

Description: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[Crack Hack] test_bench_top

Description: 用于AES加密的testbench。产生激励-AES encryption for testbench. Incentive
Platform: | Size: 10240 | Author: zsh | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[Crack Hack] RIJNDAEL_EN_TOP

Description: AES加密运算模块，运算速率100Mbps，请大家参考-AES encryption algorithms module, computing speed 100Mbps, please refer to
Platform: | Size: 16384 | Author: 刘文庆 | Hits:

[Crack Hack] aes

Description: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[VHDL-FPGA-Verilog] aes

Description: vhdl implementation of the AES encryption algorithm
Platform: | Size: 244736 | Author: hesham | Hits:

[VHDL-FPGA-Verilog] aes

Description: 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Platform: | Size: 4096 | Author: wangrui | Hits:

[VHDL-FPGA-Verilog] aesencryption

Description: Aes encryption on Fpga
Platform: | Size: 4096 | Author: Ibrahim | Hits:

[Crack Hack] AESsim

Description: AES alogrithm security encryption
Platform: | Size: 2700288 | Author: priya | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[VHDL-FPGA-Verilog] aes

Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: | Size: 87040 | Author: dinxj | Hits:

[VHDL-FPGA-Verilog] top_module

Description: AES Encryption Algorithm.... This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module-AES Encryption Algorithm.... This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module
Platform: | Size: 3072 | Author: Syed Shafi | Hits:

[VHDL-FPGA-Verilog] aes

Description: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Platform: | Size: 2973696 | Author: cong | Hits:

[VHDL-FPGA-Verilog] aes_pipe_latest.tar

Description: implementation of AES encryption algorithm in vhdl/verilog
Platform: | Size: 188416 | Author: cooldude | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
Platform: | Size: 133120 | Author: weipingzhang | Hits:

[Crack Hack] AES

Description: 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
Platform: | Size: 559104 | Author: 韩颖 | Hits:

[Crack Hack] AES-Encryption-VHDL-master

Description: AES Encryprtion an decryption algorithm
Platform: | Size: 11264 | Author: Heramban iyer | Hits:
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