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[Other resource] altera的IP源码

Description: Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
Platform: | Size: 149399 | Author: 王天权 | Hits:

[SourceCode] turbo码 IP core

Description: turbo码 IP core, VHDL编写，Altera公司的，用于信道编码中turbo码的译码
Platform: | Size: 155967 | Author: zhhzhhj@163.com | Hits:

[SourceCode] Altera IP Core

Description: 15 Altera IP Core
Platform: | Size: 49033 | Author: mayli8 | Hits:

[VHDL-FPGA-Verilog] altera的IP源码

Description: Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
Platform: | Size: 149504 | Author: 王天权 | Hits:

[VHDL-FPGA-Verilog] 发布15个Altera的IP的源码

Description: ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
Platform: | Size: 49152 | Author: 汪旭 | Hits:

[VHDL-FPGA-Verilog] 200512251221612004

Description: 本文件是altera公司fpga的ip核，从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.
Platform: | Size: 787456 | Author: 崔战 | Hits:

[ARM-PowerPC-ColdFire-MIPS] 15AlteraIPCODE

Description: 15个Altera的IP的源码，嵌入式开发必备-15 Altera IP source code, the embedded development required!
Platform: | Size: 49152 | Author: 罗军 | Hits:

[TCP/IP stack] altera_lwip

Description: 已移植到altera nios ii软核的基于microC/OS操作系统的lwip全套源代码- Transplanted to altera the nios ii soft nucleus based on microC/OS the operating system lwip complete set source code
Platform: | Size: 351232 | Author: 刘雅莎 | Hits:

[Program doc] lpm_quick_guide

Description: altera公司的fpga期间的所有lpm模块的快速设计，涵盖了全部的lpm ip模块-altera during the fpga all lpm module rapid design, cover all the ip module lpm
Platform: | Size: 532480 | Author: 江汉 | Hits:

[Software Engineering] altera+dpd

Description: 数字预失真在通信领域内IP核的开发文档，包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
Platform: | Size: 1397760 | Author: 聂华 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] Audio_DAC_FIFO

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
Platform: | Size: 15360 | Author: 朱峰 | Hits:

[Embeded-SCM Develop] DM9000A

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻易实现对dm9000a网卡的控制。-altera
Platform: | Size: 16384 | Author: 朱峰 | Hits:

[Embeded-SCM Develop] VGAControllercomponent

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻松控制vga的显示，十分难得哦！-altera
Platform: | Size: 23552 | Author: 朱峰 | Hits:

[Other] cosine_IP

Description: altera 的cosine函数 ip 核-altera the cosine function ip nuclear
Platform: | Size: 2048 | Author: 李涛 | Hits:

[Embeded-SCM Develop] i2c_IP

Description: altera 的i2c ip核，可直接调用 在quartus中把库指向文件位置就可-altera the i2c ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 7168 | Author: 李涛 | Hits:

[Other] uart_IP

Description: altera 的uart ip核，可直接调用 在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 5120 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] AteralIP

Description: Altera IP核8B10B编码器的完整设计流程包括Altera IP的定制、仿真和实现的全过程-Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
Platform: | Size: 395264 | Author: 崔慧娟 | Hits:

[Embeded-SCM Develop] Altera_IPcore

Description: 15个Altera ip核，大家可以相爱在使用-15 Altera ip
Platform: | Size: 961536 | Author: ch | Hits:

[VHDL-FPGA-Verilog] Altera_IP_verilog

Description: Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
Platform: | Size: 395264 | Author: Gorce | Hits:
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