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[Other resource] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 34569 | Author: xf | Hits:

[Embeded-SCM Develop] SRAM_Controller

Description: SRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Platform: | Size: 325227 | Author: 李大同 | Hits:

[Other resource] sdrsdramuse

Description: 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。
Platform: | Size: 701839 | Author: kurt | Hits:

[Other resource] altera_avalon_cy7c1380_ssram

Description: 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去
Platform: | Size: 7200 | Author: liufanyu | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[Embeded-SCM Develop] SRAM_Controller

Description: SRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Platform: | Size: 324608 | Author: 李大同 | Hits:

[Software Engineering] sdrsdramuse

Description: 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。-ALTERA s FPGA on a how to achieve the guidance of SDR SRAM articles. Great guiding significance.
Platform: | Size: 701440 | Author: kurt | Hits:

[Other Embeded program] altera_avalon_cy7c1380_ssram

Description: 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去-On the SRAM
Platform: | Size: 7168 | Author: liufanyu | Hits:

[Embeded-SCM Develop] sls_sram_16_bit

Description: altera NIOS软核系统中构建外接SRAM接口的例子-altera NIOS soft-core system to build external SRAM interface example
Platform: | Size: 3072 | Author: 黄杰 | Hits:

[VHDL-FPGA-Verilog] fpga_sram

Description: Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
Platform: | Size: 389120 | Author: wmy | Hits:

[VHDL-FPGA-Verilog] altera_sdram

Description: Simple SDRAM controller source code for Altera DE2 board
Platform: | Size: 7168 | Author: leblebitozu | Hits:

[ARM-PowerPC-ColdFire-MIPS] niossramflash

Description: 在altera FPGA ep3c25器件上实现niosii+sram+flash-Altera FPGA ep3c25 in devices to achieve niosii+ sram+ flash
Platform: | Size: 17807360 | Author: billfeng | Hits:

[ARM-PowerPC-ColdFire-MIPS] niossram

Description: altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板-altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board
Platform: | Size: 15242240 | Author: billfeng | Hits:

[VHDL-FPGA-Verilog] UART_DMA

Description: 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
Platform: | Size: 11346944 | Author: 王超 | Hits:

[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

Description: 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
Platform: | Size: 918528 | Author: ningning | Hits:

[VHDL-FPGA-Verilog] SRAM_Controller

Description: Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Platform: | Size: 324608 | Author: vicky | Hits:

[Software Engineering] bemicro_lab_ver

Description: be micron sram file downloaded from altera be-micro
Platform: | Size: 1024 | Author: praveen | Hits:

[Other] vhdl_sram_ctrl

Description: Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
Platform: | Size: 1024 | Author: hanhyunjin | Hits:

[VHDL-FPGA-Verilog] das3580sch

Description: das3580开发板原理图，■ Altera CycloneII EP2C8Q208C8N 的FPGA器件； ■ EPCS4 – 4Mbit 串行配置器件； ■ JTAG和AS双模式下载口； ■ 512Kbyte 10ns级SRAM器件构成双数据通道； ■ Cy7c68013a_128axc高性能USB2.0控制芯片；-das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPGA device ■ EPCS4- 4Mbit serial configuration device ■ JTAG and AS dual-mode download port ■ 512Kbyte 10ns SRAM devices constitute a dual-level data channel ■ Cy7c68013a_128axc high-performance USB2.0 control chip
Platform: | Size: 62464 | Author: 徐庆富 | Hits:

[hardware design] 添加库2

Description: 在modelsim中实现硬件库的调用，实现类似SRAM的仿真(Implement the call of the hardware Library in Modelsim and implement the simulation like SRAM)
Platform: | Size: 2276352 | Author: 雾部17 | Hits:
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