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[Other] Core8051s_HB

Description: Actel最新公布的免费微控制器IP核-Core8051S，在CoreConsole环境使用，完全兼容A51指令，具备APB总线，可配置多种外设。-Actel latest microcontroller IP core free-Core8051S, in CoreConsole environmental use, fully compatible with Directive A51 with APB bus can be configured a variety of peripherals.
Platform: | Size: 1013760 | Author: 原子 | Hits:

[VHDL-FPGA-Verilog] AMBAcode(vhdl)

Description: vhdl实现的amba代码-realize the AMBA VHDL code
Platform: | Size: 201728 | Author: sk | Hits:

[Documents] amba

Description: doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
Platform: | Size: 289792 | Author: ashish | Hits:

[VHDL-FPGA-Verilog] amba

Description: AMBA VHDL源代码.讲解的很详细，看看有什么可以借鉴的地方。-AMBA VHDL sourse
Platform: | Size: 35840 | Author: wusheer | Hits:

[ARM-PowerPC-ColdFire-MIPS] apb_bridge

Description: arm ambm 2.0 primecell算法 ahb 与 apb通讯的转换模块-arm ambm 2.0 primecell algorithm ahb conversion and communications module apb
Platform: | Size: 2048 | Author: sunk | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA_V2.0_CN

Description: ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
Platform: | Size: 1077248 | Author: 陶戈丹 | Hits:

[Other] sc_apbSlave

Description: systemc写的apb slave程序，用于实现apb总线上的slave-systemc write apb slave procedure used to implement apb bus slave
Platform: | Size: 1024 | Author: Hanshan | Hits:

[Other] RTC

Description: verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
Platform: | Size: 12288 | Author: 郭晓进 | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA

Description: 详细讲述了ARM总线体系，包括AHB，ASB，APB。-Detailed account of the ARM bus system, including AHB, ASB, APB.
Platform: | Size: 887808 | Author: John | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] a_vhdl_8253_timer_latest.tar

Description: 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
Platform: | Size: 107520 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现-iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation
Platform: | Size: 463872 | Author: 蔡搏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA-AHB-APB-BUS

Description: 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
Platform: | Size: 50176 | Author: sp | Hits:

[File Format] AHP_APB

Description: ARM公司提出的总线协议AHB和APB的中文资料，可作为参考资料-ARM s proposed AHB and APB bus protocol of the Chinese data, can be used as reference
Platform: | Size: 424960 | Author: 李菲 | Hits:

[VHDL-FPGA-Verilog] Ahb2Apb

Description: AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
Platform: | Size: 5120 | Author: local_boy | Hits:

[VHDL-FPGA-Verilog] apb.v

Description: AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
Platform: | Size: 805888 | Author: 卧室一条鱼 | Hits:

[Other] apb_uart_sv-pulpinov1

Description: SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
Platform: | Size: 16384 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
Platform: | Size: 2048 | Author: megmand | Hits:

[VHDL-FPGA-Verilog] apb_timer.tar

Description: 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
Platform: | Size: 67584 | Author: megmand | Hits:

[Other] APB_timer

Description: 设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主 机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值， 并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号， 当计数器满足模式配置后的计数要求时，会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB The computer configures the counter through the address and sets the maximum value of the counter through the data input port, And output the count value of the counter through the data output port. The design also sets a count completion signal, When the counter meets the counting requirements after the mode configuration, the signal will be pulled high)
Platform: | Size: 312320 | Author: littbi | Hits:
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