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[Other resource] Digital-video-ASIC-DISIGN1 DL : 0: 数字视频时域处理算法及其ASIC芯片设1.rar数字视频时域处理算法及其ASIC芯片设2.rar数字视频时域处理算法及其ASIC芯片设3.rar数字视频时域处理算法及其ASIC芯片设4.rar 数字视频时域处理算法及其ASIC芯片设5.rar 数字视频时域处理算法及其ASIC芯片设6.rar-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.rar time domain processing algorithms and ASIC chip located two. rar time-domain digital video processing algorithms and ASIC chip based 3. rar Digital Video time domain processing algorithms and ASIC chip located 4. rar time-domain digital video processing algorithms and ASIC chip located 5 . rar time-domain digital video processing algorithms and ASIC chip set June. rar
Date : 2008-10-13 Size : 60.92kb User : sdfafaf
[Other resource] Digital-video-ASIC-DISIGN2 DL : 0: 数字视频时域处理算法及其ASIC芯片设1.RAR 数字视频时域处理算法及其ASIC芯片设2.RAR 数字视频时域处理算法及其ASIC芯片设3.RAR 数字视频时域处理算法及其ASIC芯片设4.RAR 数字视频时域处理算法及其ASIC芯片设5.RAR数字视频时域处理算法及其ASIC芯片设6.RAR-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.RAR time domain processing algorithms and ASIC chip located two. RAR time-domain digital video processing algorithms and ASIC chip based 3. RAR Digital Video time domain processing algorithms and ASIC chip located 4. RAR time-domain digital video processing algorithms and ASIC chip located 5 . RAR time-domain digital video processing algorithms and ASIC chip set June. RAR
Date : 2008-10-13 Size : 143.86kb User : sdfafaf
[Other resource] Digital-video-ASIC-DISIGN5 DL : 0: 数字视频时域处理算法及其ASIC芯片设1.RAR 数字视频时域处理算法及其ASIC芯片设2.RAR 数字视频时域处理算法及其ASIC芯片设3.RAR 数字视频时域处理算法及其ASIC芯片设4.RAR 数字视频时域处理算法及其ASIC芯片设5.RAR数字视频时域处理算法及其ASIC芯片设6.RAR-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.RAR time domain processing algorithms and ASIC chip located two. RAR time-domain digital video processing algorithms and ASIC chip based 3. RAR Digital Video time domain processing algorithms and ASIC chip located 4. RAR time-domain digital video processing algorithms and ASIC chip located 5 . RAR time-domain digital video processing algorithms and ASIC chip set June. RAR
Date : 2008-10-13 Size : 157.17kb User : sdfafaf
[Other resource] ASIC-MP4V_VID_MPEG4_ASP DL : 0: ASIC-MP4V_VID—MPEG4 ASP标准理解。本文对MPEG4标准中的Advanced Simple Profile（ASP）做一个完整的说明，作者并不只是对标准进行翻译，而是根据他当初读标准时遇到的问题，给出一个更容易理解的阅读标准的途径。-binary tree Sort of several operations, including : the establishment of two binary sort tree node insert, delete nodes, the nodes you. For a novice structure of the data useful.
Date : 2008-10-13 Size : 281.55kb User : 张磊
[WEB Code] ASIC DL : 0: 上海交大asic设计ppt-Shanghai Jiaotong University HDL design ppt
Date : 2008-10-13 Size : 81.06kb User : 李牧天
[Develop Tools] ASIC设计教程 DL : 0: ASIC设计教程-ASIC Design Guide
Date : 2008-10-13 Size : 1.35mb User : 张雨生
[Other resource] ASIC课程讲义 DL : 0: ASIC课程讲义
Date : 2010-10-17 Size : 14.15mb User : karsentkarsent
[Software Engineering] advanced.asic.synthesis.w.synopsis DL : 1: Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.-Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Date : 2011-09-07 Size : 2.18mb User : testsb
[Documents] ASIC DL : 0: 上海交大asic设计ppt-Shanghai Jiaotong University HDL design ppt
Date : 2025-07-08 Size : 81kb User : 李牧天
[Books] ASIC设计教程 DL : 0: Date : 2025-07-08 Size : 1.35mb User : 张雨生
[VHDL-FPGA-Verilog] Sparc_leon_VHDL DL : 0: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Date : 2025-07-08 Size : 1.79mb User : 韩红
[VHDL-FPGA-Verilog] VHDL_100Examples DL : 0: 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
Date : 2025-07-08 Size : 194kb User : 韩红
[Other] ASIC-MP4V_VID_MPEG4_ASP DL : 0: ASIC-MP4V_VID—MPEG4 ASP标准理解。本文对MPEG4标准中的Advanced Simple Profile（ASP）做一个完整的说明，作者并不只是对标准进行翻译，而是根据他当初读标准时遇到的问题，给出一个更容易理解的阅读标准的途径。-binary tree Sort of several operations, including : the establishment of two binary sort tree node insert, delete nodes, the nodes you. For a novice structure of the data useful.
Date : 2025-07-08 Size : 281kb User : 张磊
[Other] advanced.asic.synthesis.w.synopsis DL : 0: Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.-Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Date : 2025-07-08 Size : 2.18mb User : eioruqoiu
[Other] ASIC DL : 0: 介绍专用集成电路设计的一本书，很有参考价值，适合高年级本科生和研究生-Introduction ASIC design a book, a good reference for senior undergraduate and postgraduate
Date : 2025-07-08 Size : 3.29mb User : lql
[Software Engineering] ASIC DL : 0: ASIC完整设计实例，帮助初学者了解ASIC的设计流程-Complete ASIC design to help beginners understand the ASIC design flow
Date : 2025-07-08 Size : 1.63mb User : mars
[Other] Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design DL : 0: 使用synopsys design compiler和 prime time进行Asic开发的英文pdf-Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler.Physical.Compiler.And.Primetime
Date : 2025-07-08 Size : 3.89mb User : rocky
[Windows Develop] ASIC DL : 0: 一個完整ASIC流程的說明文件，讓你完全了解IC Design Flow-ASIC Flow Document
Date : 2025-07-08 Size : 1.36mb User : 李昆憲
[VHDL-FPGA-Verilog] ASIC-SYNOPSYS DL : 0: 芯片设计综合经典书籍 design compiler primetime-asic synthesys
Date : 2025-07-08 Size : 2.14mb User : yin zhigang
[Other] ASIC 2011 Chapter 8 Verification and Testing DL : 0: SoC专用集成电路的验证设计，使用Verilog语言。(Verification of ASIC SoC project with Verilog HDL langauge.)
Date : 2025-07-08 Size : 2.86mb User : renminggong

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