Search - AXI VHDL

Search - AXI VHDL - List

[VHDL-FPGA-Verilog] adma.tar DL : 0: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Update : 2025-02-17 Size : 12kb Publisher : maliang
[VHDL-FPGA-Verilog] 15-IP-core DL : 0: 15个免费的IP核 IP核源代码 -15 IP cores
Update : 2025-02-17 Size : 4.37mb Publisher : chris
[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar DL : 0: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Update : 2025-02-17 Size : 306kb Publisher : 李忠孝
[Other] apb_slave DL : 1: AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
Update : 2025-02-17 Size : 1kb Publisher : Henry
[VHDL-FPGA-Verilog] Axi_mux DL : 0: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Update : 2025-02-17 Size : 41kb Publisher : Paul Stephen
[VHDL-FPGA-Verilog] ppt DL : 0: 介绍 AXI 协议的PPT, 和一个 slave（verilog实现）接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Update : 2025-02-17 Size : 623kb Publisher : 周西东
[VHDL-FPGA-Verilog] std_ovl_v2p7_Feb2013 DL : 0: 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
Update : 2025-02-17 Size : 4.79mb Publisher : 张无忌
[Other] axi_master_latest.tar DL : 0: axi 总线设计和仿真，可以在设计中直接运动，提供完整源代码和仿真文件，用vhdl 语言实现。-axi bus design and simulation, you can directly exercise in design, providing full source code and simulation files, using vhdl language.
Update : 2025-02-17 Size : 18kb Publisher : hc
[VHDL-FPGA-Verilog] microzed-axi-dma DL : 0: microzed (zynq) axi dma source vhdl
Update : 2025-02-17 Size : 20kb Publisher : ulsonic
[VHDL-FPGA-Verilog] axi_jesd204b DL : 1: ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
Update : 2025-02-17 Size : 76kb Publisher : Eddie