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[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] Computer Architecture Handbook on Verilog HDL

Description: Computer Architecture Handbook on Verilog HDL
Platform: | Size: 66560 | Author: 路路 | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[SCM] STC89C51RCRD+系列内部 EEPROM 放数据(C语言) _c

Description: STC89C51RCRD+系列内部 EEPROM存放数据(C语言)，此款单片机可是物美价廉啊！！！ -STC89C51RCRD series of internal EEPROM data storage (C language) says the Catholic SCM But ah! ! !
Platform: | Size: 5120 | Author: 经济学 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio/video codec
Platform: | Size: 222208 | Author: | Hits:

[VHDL-FPGA-Verilog] 7_4859_1

Description: 卡内基梅陇大学verilog课程讲义,希望大家能够喜欢！-Verilog University of Paisley and Adams Carnegie Course Training Manual, we hope to love!
Platform: | Size: 234496 | Author: 张新 | Hits:

[Books] Verilog_HDL_Hardware_Description_Language

Description: 正式出版物《Verilog HDL 硬件描述语言》一书的精美 PDF 电子版。-official publications "Verilog HDL Hardware Description Language," a book of exquisite electronic PDF version.
Platform: | Size: 4767744 | Author: bigheadmonk | Hits:

[ARM-PowerPC-ColdFire-MIPS] AUDIO_DAC

Description: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Platform: | Size: 2048 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Platform: | Size: 26624 | Author: 李全 | Hits:

[Audio program] WM8731

Description: 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
Platform: | Size: 7168 | Author: 李全 | Hits:

[Other] demultiplex

Description: 是用verilog写的,解复接程序,可以把复接的反过来,一般用在解码程序中!-verilog is written, Demultiplexer procedures can multiplexing the contrary, generally used in the decoding process.
Platform: | Size: 162816 | Author: lw234620 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章 数字信号处理、计算、程序、 算法和硬线逻辑的基本概念 第二章 Verilog HDL设计方法概述 第三章 Verilog HDL的基本语法 第四章 不同抽象级别的Verilog HDL模型 第五章 基本运算逻辑和它们的Verilog HDL模型 第六章 运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[MiddleWare] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232448 | Author: wjz | Hits:

[Editor] verilog_source_insight_clf

Description: SOURCE INSIGHT的verilog语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT verilog syntax of plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers
Platform: | Size: 3072 | Author: 洪炉 | Hits:

[Special Effects] djpeg_vlsi

Description: jpeg解码电路，是verilog编写的，可以综合，很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
Platform: | Size: 181248 | Author: blueli | Hits:

[ARM-PowerPC-ColdFire-MIPS] sarm9beta

Description: arm9 架构简单core实现，可以综合，有实现步骤和说明，verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
Platform: | Size: 951296 | Author: blueli | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7_core_verilog

Description: arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
Platform: | Size: 677888 | Author: blueli | Hits:

[VHDL-FPGA-Verilog] ADC_16bit

Description: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
Platform: | Size: 1024 | Author: awp | Hits:

[VHDL-FPGA-Verilog] mipsinverilogandvhdl

Description: mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
Platform: | Size: 7168 | Author: 张六封 | Hits:
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