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Other resource
Title:
9.16fifoasi
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2.63mb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
einyang
Description:
the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Downloaders recently:
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More information of uploader einyang
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To Search:
Verilog TV
C Verilog
verilog
fifo verilog
buffer verilog
FIFO
verilog fifo
fifoasi
fifo vhdl
Verilog Source code
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oci
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imagescaler
] - eight or 24 images zoom module, support
[
circularbuffer
] - Circular_Buffer, type a number of buffer
[
transport_stream_analyzer_v1.73
] - transport stream analyzer can analyze TS
[
fifo
] - A First in first out buffer in Verilog
[
VIDEO-FPGA
] - Video Capture output examples
[
FIFO
] - FIFO control in the FPGA
[
DE2_TV
] - Based on DE-2 board TV- box development,
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