Search - CAN Controller Veril

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[ARM-PowerPC-ColdFire-MIPS] mem_ctrl.tar DL : 0: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Update : 2025-02-17 Size : 324kb Publisher : youjia
[VHDL-FPGA-Verilog] ac97_verilog_sourcecode DL : 1: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Update : 2025-02-17 Size : 122kb Publisher : 小步
[VHDL-FPGA-Verilog] 8259 DL : 0: 这是一个中断控制器的IP，功能很全，可以直接使用，类似于INTEL的8259，作为中断扩展。-This is an interrupt controller of the IP, is the whole function can be used directly, similar to INTEL in 8259, as extended interruption.
Update : 2025-02-17 Size : 2kb Publisher : kristing
[Other Embeded program] SRAMCotroller DL : 0: 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Update : 2025-02-17 Size : 315kb Publisher : liufanyu
[VHDL-FPGA-Verilog] can.tar DL : 0: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Update : 2025-02-17 Size : 53kb Publisher : yu
[VHDL-FPGA-Verilog] CAN_IP DL : 1: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Update : 2025-02-17 Size : 60kb Publisher : 普林斯
[VHDL-FPGA-Verilog] can_verilog_source DL : 0: verilog code for can controller
Update : 2025-02-17 Size : 46kb Publisher : subha