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Description: verilog码写的CIC滤波器的程序,包括4倍抽取CIC滤波器和内插的CIC滤波器两个
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Size: 22698 |
Author: 桃子 |
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Description: 用于dspbuilder 可以直接生成vhdl源码,或者verilog源码
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Size: 40594 |
Author: wq |
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Description: cic code选用verilog代码编写
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Size: 2629 |
Author: flcan@163.com |
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Description: 介绍了积分梳状滤波器(CIC)设计,压缩包里面有程序的流程图,采用verilogHDL编写,在modelsim上可以实现仿真结果,非常不错-Introduced the integral comb filter (CIC) design, there are procedures for compressed packets flow chart, using verilogHDL prepared on the ModelSim simulation results can be achieved very good
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Size: 153600 |
Author: yaoyongshi |
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Description: 一个3阶的32位抽取的cic滤波器的verilog源代码-A 3-bands of the 32 samples CIC filter Verilog source code
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Size: 1024 |
Author: 岑楠 |
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Description: verilog码写的CIC滤波器的程序,包括4倍抽取CIC滤波器和内插的CIC滤波器两个-Verilog code written by CIC filter procedures, including 4 times the extraction CIC filter and the CIC interpolation filter two
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Size: 22528 |
Author: 桃子 |
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Description: 本文讲解CIC数字滤波器的设计,对设计者有很大的帮助-This article on the CIC digital filter design, for designers of great help
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Size: 129024 |
Author: asdtgg |
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Description: 单级CIC2倍内插滤波器,用verilogHDL实现-CIC2 times the single-stage interpolation filter, used to achieve verilogHDL
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Size: 498688 |
Author: Carl |
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Description: CIC滤波器源码,有VERILOG写的,非常有用哦-CIC filter source code, Verilog has written a very useful Oh
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Size: 2048 |
Author: 刘记名 |
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Description: 阶的32倍抽取cic滤波器verilog代码-Order CIC filter 32 times the extraction Verilog code
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Size: 1024 |
Author: zly |
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Description: 实现4倍抽取的CIC抽取滤波器模块的Verilog实现,在对数据进行抽取之前,首先进行滤波-Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter
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Size: 1024 |
Author: 楚鹤 |
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Description: 用于dspbuilder 可以直接生成vhdl源码,或者verilog源码-用于dspbuilder ?梢灾 ??由??蓈hdl?
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Size: 39936 |
Author: wq |
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Description: 积分梳状滤波器(CIC)verilog设计.rar-Integral comb filter verilog design.rar
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Size: 1024 |
Author: 海天之洲 |
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Description: CIC梳状滤波器verilog源码,包括积分器,下抽级以及梳状滤波器三个部分。-CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
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Size: 1024 |
Author: 张佳培 |
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Description: CIC抽取滤波器,抽取系数8,verilog版本,用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
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Size: 1024 |
Author: 王刚 |
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Description: 抽取滤波的Verilog实现,经测试可用-Decimation filter
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Size: 1024 |
Author: anderson |
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Description: 3阶的32倍抽取cic滤波器verilog代码-Level 3, 32 times the extraction of cic filter verilog code
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Size: 1024 |
Author: |
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Description: cic设计 verilog -cic verilog design verilog
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Size: 1024 |
Author: 孙累 |
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Description: 该文件包含数字抽取滤波器cic的verilog代码,经测试可用,且简介,消耗硬件资源较少。-This file contains digital sampling filter cic verilog code, after testing is available, and the introduction, less consumption of hardware resources.
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Size: 1024 |
Author: 张俊 |
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Description: Code Verilog CIC Filter FPGA
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Size: 646144 |
Author: MrGio
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