Location:
Search - CORDIC .v
Search list
Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: |
Size: 12917 |
Author: 郝晋 |
Hits:
Description: cordic IP core
Features
Each file is stand-alone and represents a specific configuration.
The 4 parameters are:
Rotation or Vector Mode
Vector Precision
Angle Precision
Number of Cordic Stages
All designs are pipelined with a synchronous enable and reset.
The pipeline latency equals 2 clock cycles plus the number of cordic stages.
The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v
r : Cordic Mode. r = Rotation, v = Vectoring
32 : Precision of the individual vector components.
16 : Precision of the angle.
12 : Number of cordic stages.
Current configurations:
cf_cordic_r_8_8_8
cf_cordic_v_8_8_8
cf_cordic_r_16_16_16
cf_cordic_v_16_16_16
cf_cordic_r_18_18_18
cf_cordic_v_18_18_18
cf_cordic_r_32_32_32
cf_cordic_v_32_32_32
Platform: |
Size: 458196 |
Author: abcoabco |
Hits:
Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Platform: |
Size: 221184 |
Author: 李文文 |
Hits:
Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: |
Size: 12288 |
Author: 郝晋 |
Hits:
Description: cordic算法的Verilog HDL具体实现-CORDIC algorithm specific realize Verilog HDL
Platform: |
Size: 7168 |
Author: 王伟 |
Hits:
Description: Altera公司的CORDIC开发包,用Verilog编写的,安装在Quartus相同目录中,里面有详细的开发说明。-Altera
Platform: |
Size: 1355776 |
Author: YangJun |
Hits:
Description: 数字计算机的设计coric,利用 verilog实现,格式为.v格式.详细见文件注释-The design of digital computers coric, the realization of the use of Verilog format. V format. Detailed document Notes
Platform: |
Size: 1024 |
Author: oasis |
Hits:
Description: cordic IP core
Features
Each file is stand-alone and represents a specific configuration.
The 4 parameters are:
Rotation or Vector Mode
Vector Precision
Angle Precision
Number of Cordic Stages
All designs are pipelined with a synchronous enable and reset.
The pipeline latency equals 2 clock cycles plus the number of cordic stages.
The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v
r : Cordic Mode. r = Rotation, v = Vectoring
32 : Precision of the individual vector components.
16 : Precision of the angle.
12 : Number of cordic stages.
Current configurations:
cf_cordic_r_8_8_8
cf_cordic_v_8_8_8
cf_cordic_r_16_16_16
cf_cordic_v_16_16_16
cf_cordic_r_18_18_18
cf_cordic_v_18_18_18
cf_cordic_r_32_32_32
cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: |
Size: 457728 |
Author: abcoabco |
Hits:
Description: 基4快速傅里叶变换,涉及cordic算法,可以用来学习-fft
Platform: |
Size: 82944 |
Author: sun |
Hits: