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Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
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Size: 1012462 |
Author: 李华 |
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Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
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Size: 4731904 |
Author: 李华 |
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Description:
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Size: 490496 |
Author: liuxingxing |
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Description: 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
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Size: 13312 |
Author: 站长 |
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Description: FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
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Size: 132096 |
Author: pengqianqian |
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Description: usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
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Size: 6144 |
Author: 牟娇 |
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