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[Embeded-SCM Developcpu

Description: vhd语言,简单cpu程序实例,包含所有源码文件。
Platform: | Size: 2796608 | Author: 阿若有 | Hits:

[VHDL-FPGA-VerilogmaxII16_cpu

Description: maxII16_cpu,altera的maxII系列的16位cpu-maxII16_cpu, altera the maxII series of 16 cpu
Platform: | Size: 220160 | Author: lrt | Hits:

[VHDL-FPGA-Verilogi211_001

Description: Dallas 1-Wire ip 非常有用,不占用CPU的时间.-Dallas 1-Wire ip very useful, do not occupy CPU time.
Platform: | Size: 5120 | Author: hjy | Hits:

[Embeded-SCM Developcpu

Description: vhd语言,简单cpu程序实例,包含所有源码文件。-vhd language, simple cpu instance, contains all the source documents.
Platform: | Size: 2796544 | Author: 阿若有 | Hits:

[Embeded Linuxcpu_simulation

Description: thats the CPU source made by JI FENG
Platform: | Size: 12288 | Author: FLY | Hits:

[VHDL-FPGA-Verilog8080cpu

Description: this code for cpu 8080 design -this is code for cpu 8080 design
Platform: | Size: 9216 | Author: minh | Hits:

[VHDL-FPGA-VerilogVHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[VHDL-FPGA-Verilogmips

Description: 一个单周期流水CPU的实现,其中mips4.vhd是顶层文件-A single cycle CPU
Platform: | Size: 1598464 | Author: 乔嘉林 | Hits:

[hardware designidwt

Description: Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse CPU Usage: 1435 ms
Platform: | Size: 2048 | Author: farrokh | Hits:

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