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Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ...
-Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar] - 4 division of vhdl source [vh dl example. rar] - highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
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Size: 838 |
Author: 张瑞 |
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Description: 基于VHDL的POC接口控制器,用于CPU与打印机间的数据控制-based on the POC VHDL interface controller, CPU and printer for the data control
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Size: 83968 |
Author: marscr |
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Description: maxII16_cpu,altera的maxII系列的16位cpu-maxII16_cpu, altera the maxII series of 16 cpu
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Size: 220160 |
Author: lrt |
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Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ...
-Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
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Size: 1024 |
Author: 张瑞 |
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Description: 用VHDL编写的简单POC（并行输出控制）程序，可以实现CPU以及外设之间的接口功能-Use VHDL to prepare a simple POC (parallel output control) procedures, can be achieved between the CPU and peripheral interface functions
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Size: 843776 |
Author: 匡木 |
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Description: 可以实现CPU的VHDL源码，可以在FPGA上运行-CPU can realize the VHDL source code can be run in FPGA
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Size: 1651712 |
Author: chen |
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Description: vhdl代码
使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
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Size: 1024 |
Author: 闵瑞鑫 |
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Description: 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据
自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口，
11位地址总线。支持IO 的置位清除功能。-The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
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Size: 2048 |
Author: tianrongcai |
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Description: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
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Size: 3028992 |
Author: kevin |
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