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[Other resource] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key -- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424510 | Author: 呈一 | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[Program doc] spt

Description: FIR的优化设计 基于CSD码量化 提出了一种降低滤波器运算量的改进方法-Optimal design of FIR based on CSD code to quantify a lower filter to improve the method of computing the amount of
Platform: | Size: 791552 | Author: lvxiaobing | Hits:

[Other] FIR_csd_mul

Description: 采用CSD编码的常系数乘法器的FIR滤波器的设计。-CSD-coded using constant coefficient multipliers of the FIR filter design.
Platform: | Size: 9216 | Author: 敬礼 | Hits:

[VHDL-FPGA-Verilog] filter1

Description: 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hope it would be useful
Platform: | Size: 13312 | Author: 万勇 | Hits:

[VHDL-FPGA-Verilog] 20FIRfilterwithCSD

Description: 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
Platform: | Size: 3072 | Author: zhuhui | Hits:

[VHDL-FPGA-Verilog] 20FIRFilterDecimal

Description: 20阶FIR数字滤波器，参数没有进行倍数扩大，参数经过CSD编码处理-20-order FIR digital filter, the parameter no multiple expansion, parameter encoding process after CSD
Platform: | Size: 2048 | Author: zhuhui | Hits:

[VHDL-FPGA-Verilog] CSDmultiplier

Description: Code for CSD Multiplier
Platform: | Size: 1024 | Author: yuvi | Hits:

[matlab] CSDcodingbasedFIR

Description: 基于CSD编码的FIR数字滤波器优化设计（使用MATLAB程序）-CSD coding based FIR digital filter design (using the MATLAB program)
Platform: | Size: 264192 | Author: xiaoyuehaome | Hits:

[OS program] fcsdnew

Description: Factored CSD based FIR filter
Platform: | Size: 1524736 | Author: neha | Hits:

[VHDL-FPGA-Verilog] fir25

Description: 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit of hardware requirements), which calls the multiplier official API, can be used to save resources CSD encoding conversion multiplier can be reduced by more than half of the resources
Platform: | Size: 1024 | Author: wangjin | Hits:

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