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[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[VHDL-FPGA-Verilog] 16_FIR

Description: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Platform: | Size: 799744 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] verilog.DA.FIR..

Description: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Platform: | Size: 576512 | Author: 代鑫 | Hits:

[VHDL-FPGA-Verilog] DA_FIR_VERILOG

Description: 基于DA算法的FIR滤波器的verilog实现-DA-based FIR filter algorithm to achieve the verilog
Platform: | Size: 1024 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] FIRde-verilog-shixian

Description: 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
Platform: | Size: 4096 | Author: 紫微 | Hits:

[VHDL-FPGA-Verilog] verilog-fir

Description: 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
Platform: | Size: 2048 | Author: | Hits:

[Other] da_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） ​ 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。​ 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能，采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA)，将MAC运算转化为查找表(Look-Up-Table, LUT)输出，不仅能在硬件规模上得到改善，而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器，并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[Other Embeded program] FIR32

Description: 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
Platform: | Size: 3072 | Author: Awei | Hits:

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