Search - DDR2 vhdl

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[OS program] ddr2 VHDL原代码 DL : 0: ddr2的仿真代码
Update : 2009-09-02 Size : 813.8kb Publisher : kabtechnology@126.com
[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237 DL : 0: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Update : 2025-02-17 Size : 203kb Publisher : 上面的
[Graph Drawing] VGAsingl DL : 0: fpga显示控制器，利用vhdl语言实现，只能显示8色。-fpga display controller, using vhdl language, the only shows that eight colors.
Update : 2025-02-17 Size : 1kb Publisher : lyc
[Compress-Decompress algrithms] DDR2_sdram DL : 0: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Update : 2025-02-17 Size : 944kb Publisher : 李国
[VHDL-FPGA-Verilog] DDR2_module_VHDL_test(Rev0.1) DL : 0: ddr 2 接口读写测试模块 ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Update : 2025-02-17 Size : 123kb Publisher : 骑士
[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0 DL : 0: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Update : 2025-02-17 Size : 1.61mb Publisher : li ji wei
[VHDL-FPGA-Verilog] vga_control DL : 0: vga 控制器的verilog 源码，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
Update : 2025-02-17 Size : 1kb Publisher : zys
[VHDL-FPGA-Verilog] DDR2Controller DL : 0: DDR2 Controller DDR2 Controller
Update : 2025-02-17 Size : 305kb Publisher : tg
[VHDL-FPGA-Verilog] ddr2sdram_spartan3s700an.tar DL : 0: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working.
Update : 2025-02-17 Size : 1.42mb Publisher : under
[Other] CODE DL : 0: DDR2源代码 DDR2源代码-ddr2 source code ddr2 source code ddr2 source code
Update : 2025-02-17 Size : 292kb Publisher : 司炯
[Other] Micron_DDR DL : 0: DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
Update : 2025-02-17 Size : 422kb Publisher : robert.wang
[VHDL-FPGA-Verilog] s3ask_ddr2 DL : 0: DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Update : 2025-02-17 Size : 2.49mb Publisher : Joe Zhu
[VHDL-FPGA-Verilog] c_xapp454 DL : 0: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Update : 2025-02-17 Size : 212kb Publisher : 陈阳
[Compress-Decompress algrithms] 49636967xapp935 DL : 0: DDR2驱动方面的资料,很有用的。希望对大家有用-drive of DDR2
Update : 2025-02-17 Size : 339kb Publisher : 王川
[VHDL-FPGA-Verilog] LPC2DDR2 DL : 0: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Update : 2025-02-17 Size : 8kb Publisher : 吴羽中
[VHDL-FPGA-Verilog] ddr2_controller DL : 0: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Update : 2025-02-17 Size : 51kb Publisher : yanxp
[VHDL-FPGA-Verilog] mcb_read_write DL : 0: 赛灵思 DDR2 用户接口程序原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
Update : 2025-02-17 Size : 2kb Publisher : wenchunhong
[VHDL-FPGA-Verilog] OK16bit DL : 0: 16BITS DDR2原理图讲解详细学习用
Update : 2025-02-17 Size : 152kb Publisher : zhangfuquan
[VHDL-FPGA-Verilog] DDR2_16bit DL : 0: ddr2原理图设计，原厂电路图设计，很好很强大 16bit-ddr2 schematic design, the original schematic design, a very powerful 16bit
Update : 2025-02-17 Size : 152kb Publisher : 田云钧
[VHDL-FPGA-Verilog] ddr2 DL : 0: ddr2的功能控制模块，3部分，只要调取就可以。-ddr2 control codes
Update : 2025-02-17 Size : 5kb Publisher : wenxin

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