Search - DDR2 controller

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[Other] u26a_spice DL : 0: ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
Update : 2025-02-17 Size : 291kb Publisher :
[VHDL-FPGA-Verilog] xapp935 DL : 0: ddr2 controller, verilog source code from xilinx
Update : 2025-02-17 Size : 339kb Publisher : Hubert
[Compress-Decompress algrithms] DDR2_sdram DL : 0: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Update : 2025-02-17 Size : 944kb Publisher : 李国
[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0 DL : 0: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Update : 2025-02-17 Size : 1.61mb Publisher : li ji wei
[VHDL-FPGA-Verilog] DDR2Controller DL : 0: DDR2 Controller DDR2 Controller
Update : 2025-02-17 Size : 305kb Publisher : tg
[Embeded-SCM Develop] ddr_ddr2_sdram DL : 0: 基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.-NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
Update : 2025-02-17 Size : 3.33mb Publisher : Jackie
[VHDL-FPGA-Verilog] 1189152740 DL : 0: DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve
Update : 2025-02-17 Size : 83kb Publisher : 白皓
[Other Embeded program] Intel-IOP341-DDR2-memory-controller-initializtion. DL : 1: 可以基于本流程了解IOP Raid处理器在启动时对DDR2内存控制器的初始化。也可以以此了解其他片上系统的DDR2控制器的启动方法。-Understanding of this process can be based on IOP Raid processor at boot time on the DDR2 memory controller initialization. Can also be used to understand the other system-on-chip DDR2 controller start-up method.
Update : 2025-02-17 Size : 76kb Publisher : youxiaoguang
[VHDL-FPGA-Verilog] ddr2 DL : 0: 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Update : 2025-02-17 Size : 2.66mb Publisher : Zhao Bill
[VHDL-FPGA-Verilog] c_xapp260 DL : 0: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Update : 2025-02-17 Size : 1.07mb Publisher : 陈阳
[VHDL-FPGA-Verilog] ddr2_controller DL : 0: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Update : 2025-02-17 Size : 51kb Publisher : yanxp
[VHDL-FPGA-Verilog] AMBA DL : 0: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Update : 2025-02-17 Size : 205kb Publisher : guoxiaojin
[VHDL-FPGA-Verilog] Xil3SD1800A_MIG DL : 0: 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
Update : 2025-02-17 Size : 1.16mb Publisher : sonicecho
[VHDL-FPGA-Verilog] DDR2_controller DL : 0: DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
Update : 2025-02-17 Size : 1.73mb Publisher : alins
[VHDL-FPGA-Verilog] ddr2_test DL : 0: 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
Update : 2025-02-17 Size : 10.37mb Publisher : 左洪成
[VHDL-FPGA-Verilog] The-Speedy-DDR2-Controller- DL : 0: The Speedy DDR2 Controller For FPGAs ERSA 2009 Final
Update : 2025-02-17 Size : 165kb Publisher : 郭振宇
[VHDL-FPGA-Verilog] DDR2_Memory_Test DL : 0: DDR2 controller which contains verilog files，pdf and so on
Update : 2025-02-17 Size : 229kb Publisher : zhang
[Software Engineering] TMS320DM646x--DDR2-Controller- DL : 0: TMS320DM646x DDR2 Memory DDR2控制器指导说明-TMS320DM646x DMSoC DDR2 Memory Controller User s Guide (Rev. C)(sprueq4c).rar
Update : 2025-02-17 Size : 330kb Publisher : 王乐
[VHDL-FPGA-Verilog] ddr2 DL : 0: leon3系统中ddr2控制器的相关代码（还包包括存储器的仿真模型），该控制器可以与amba2.0的ahb总线相连，机构比较复杂，代码量很大-ddr2 controller code (package includes the memory of the simulation model) leon3 system, the controller can with amba2.0 the ahb bus connected to more complex institutions, the amount of code
Update : 2025-02-17 Size : 214kb Publisher : 张鹏
[VHDL-FPGA-Verilog] ddr2 DL : 0: 基于xilinx spartan -3A DSP的ddr2控制器-Based on the Xilinx Spartan-3A DSP DDR2 controller
Update : 2025-02-17 Size : 11.57mb Publisher : 朱义

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