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[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

Description: quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Platform: | Size: 29696 | Author: wcm | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG

Description: 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
Platform: | Size: 1213440 | Author: sonicecho | Hits:

[VHDL-FPGA-Verilog] ddr2_mem

Description: DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行！-DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
Platform: | Size: 6144 | Author: yan | Hits:

[Other Embeded program] Xilinx_DDR2_IP_TEST

Description: 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed description. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Platform: | Size: 503808 | Author: 刘明 | Hits:

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