Search - DDS FPGA VHDL

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Platform: | Size: 5120 | Author: 胡玉贵 | Hits:

[Communication-Mobile] DDFS_PLL_10DA_with51

Description: FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
Platform: | Size: 627712 | Author: huang | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Platform: | Size: 3072 | Author: dsf | Hits:

[VHDL-FPGA-Verilog] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Platform: | Size: 88064 | Author: martin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Platform: | Size: 2098176 | Author: wade | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Platform: | Size: 1086464 | Author: liulei | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器-In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
Platform: | Size: 351232 | Author: ice | Hits:

[VHDL-FPGA-Verilog] dds

Description: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Platform: | Size: 571392 | Author: wangjian | Hits:

[Program doc] FPGA-DDS-FM

Description: DDS 调频信号发生器框图设计原理，有仿真测试结果-DDS signal generator FM Design Principle diagram
Platform: | Size: 69632 | Author: chenjiwei | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
Platform: | Size: 1544192 | Author: ZHANGLONG | Hits:

[VHDL-FPGA-Verilog] DDS-FPGA

Description: 基于FPGA的DDS资料！个人搜集的可直接编译-FPGA-based DDS information!
Platform: | Size: 6350848 | Author: eva | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 这是基于FPGA的直接数字频率合成器的程序，是VHDL语言-This is based on FPGA for direct digital frequency synthesizer program that is VHDL language
Platform: | Size: 1253376 | Author: 笙箫 | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

« 12 3 4 5 6 7 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Communication] Project1-DDS

[VHDL-FPGA-Verilog] DDS

[Communication-Mobile] DDFS_PLL_10DA_with51

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] vhdl-dds

[VHDL-FPGA-Verilog] dds

[Software Engineering] DDS

[VHDL-FPGA-Verilog] FPGA_signal_general

[VHDL-FPGA-Verilog] FPGA

[VHDL-FPGA-Verilog] dds

[Books] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[Program doc] FPGA-DDS-FM

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS-FPGA

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] vhdl-ad9910

CodeBus www.codebus.net