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[Consoledpll界面程序

Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序,请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Platform: | Size: 4081 | Author: zhangfj_99 | Hits:

[VHDL-FPGA-Verilog数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[matlabDPLL

Description: 数字锁相环DPLL实例程序,帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
Platform: | Size: 1024 | Author: 李向坤 | Hits:

[Consoledpll界面程序

Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序,请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Platform: | Size: 4096 | Author: | Hits:

[Books复件 数字锁相环程序

Description: 数字锁相环DPLL源程序,用cpld编写,展开后文件比较多,大家请耐心使用。谢谢,多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: | Size: 120832 | Author: | Hits:

[matlabDPLL1lp

Description: 频带数字通信中,频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Platform: | Size: 8192 | Author: rossi | Hits:

[Books060107[1].pdf

Description: 全数字锁相环,包括DPD,DLF,DCO.-DPLL, including the DPD, DLF, the making.
Platform: | Size: 89088 | Author: 熊静 | Hits:

[RFIDdigitalPLL

Description: 数字锁相环实现源码,有很大的参考价值。 由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and subtraction to establish surveillance mode N divider circuit constituted.
Platform: | Size: 2048 | Author: sharny | Hits:

[Applicationsdpll

Description: 数字锁相环,采用costas环的数字形式,实现跟踪载波相位,-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
Platform: | Size: 1024 | Author: lily | Hits:

[Windows Developdpll

Description: Quantization effect on a 2nd order DPLL design When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
Platform: | Size: 1024 | Author: dairy | Hits:

[matlab11112323

Description: 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型,并用SIMULINK对数字锁相环的仿真模型进行仿真。 -Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locked loop SIMULINK simulation model simulation.
Platform: | Size: 198656 | Author: 王利华 | Hits:

[3G developdpll

Description: DPLL SIMULATION in MATLAB
Platform: | Size: 1024 | Author: Bhavin | Hits:

[OtherPLL_grt_rtw

Description: C语言实现了数字锁相环的程序,不过程序比较复杂,得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
Platform: | Size: 24576 | Author: 蔡科 | Hits:

[DSP programdpll

Description: Digital Phase Locked Loop M-File
Platform: | Size: 1024 | Author: bumclouds2 | Hits:

[matlabdpll

Description: 应用matlab设计D触发器型的锁相环的设计的程序并对相位很频率进行性能图形比较-matlab desire Dpll
Platform: | Size: 1024 | Author: 赵红玉 | Hits:

[matlabdpll_m

Description: DPLL implementation in matlab
Platform: | Size: 1024 | Author: p2p001 | Hits:

[matlabdpll

Description: 数字锁相环,这里有个例子,可以借鉴看看,用simulink搭建的-dpll
Platform: | Size: 11264 | Author: Shane | Hits:

[Software EngineeringMatlab-about-pll

Description: 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable to all-digital phase-locked loop DPLL layout SPICE simulation, with the The model simulation results verified.
Platform: | Size: 259072 | Author: dashu | Hits:

[Books一种UPS的数字化锁相及旁路检测和切换控制技术

Description: UPS锁相环Matlab/simulink仿真(dpll Matlab/simulink)
Platform: | Size: 176128 | Author: 小线圈 | Hits:

[matlabpll

Description: 基于matlab的数字pll实现,鉴相器,滤波器以及压控震荡器组成,具备良好的锁相功能,适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
Platform: | Size: 17408 | Author: qiya2 | Hits:
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