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[Console] dpll界面程序

Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Platform: | Size: 4081 | Author: zhangfj_99 | Hits:

[Communication-Mobile] pll_improvement

Description: 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
Platform: | Size: 102669 | Author: 李敏 | Hits:

[Documents] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93479 | Author: li | Hits:

[Windows Develop] dpll

Description: Quantization effect on a 2nd order DPLL design When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
Platform: | Size: 1240 | Author: dairy | Hits:

[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[Console] dpll界面程序

Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Platform: | Size: 4096 | Author: | Hits:

[Communication-Mobile] pll_improvement

Description: 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
Platform: | Size: 102400 | Author: 李敏 | Hits:

[VHDL-FPGA-Verilog] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 167936 | Author: 李湘鲁 | Hits:

[Wavelet] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93184 | Author: li | Hits:

[Books] changyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793600 | Author: 1 | Hits:

[Software Engineering] DPLL_Circuit

Description: 本文在说明全数字锁相环的基础上，提出了一种利用FPGA设计一阶全数字锁相环的方法，并 给出了关键部件的RTL可综合代码，并结合本设计的一些仿真波形详细描述了数字锁相环的工作过程，最后对一些有关的问题进行了讨论。-In this paper, that all-digital phase-locked loop based on a FPGA design using first-order DPLL method, and gives the key components of the RTL code can be integrated and combined with the design of some of the detailed simulation waveform describes the working process of digital phase-locked loop, the last of some related issues were discussed.
Platform: | Size: 286720 | Author: wangyunshann | Hits:

[Windows Develop] dpll

Description: Quantization effect on a 2nd order DPLL design When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
Platform: | Size: 1024 | Author: dairy | Hits:

[Other] DPLL

Description: 一种可编程的全数字锁相环的丝线,可以用来做一个小的课程设计-A programmable DPLL thread can be used to do a small course design
Platform: | Size: 140288 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[Other] dpll

Description: 锁相环的基本原理，设计结构，及实现过程介绍-The basic principles of phase-locked loop, design structure, and the realization of the process of introducing
Platform: | Size: 1664000 | Author: 张兆伟 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[VHDL-FPGA-Verilog] FPGA-based-design-of-DPLL

Description: 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
Platform: | Size: 416768 | Author: 阿啊 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。-This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.
Platform: | Size: 437248 | Author: 小吴 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 数字锁相环（DPLL）的介绍与硬件实现设计-Introduction and hardware design of Digital PLL (DPLL)
Platform: | Size: 1366016 | Author: BenQlin | Hits:

[hardware design] dpll源程序

Description: 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.)
Platform: | Size: 1024 | Author: 和风5254 | Hits:
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