数字锁相环 digital phase-locked loop PLL design source,

Title: 数字锁相环

Category:
VHDL-FPGA-Verilog
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File Size:
122.26kb
Update:
2008-10-13
Downloads:
1 Times
Uploaded by:
dragongray

Description: digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF

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