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[Embeded-SCM Develop] freecore_ahdl

Description: 免费的AHDL模块库,包括IIC控制器,DRAM控制器,UART等28个模块,AHDL源代码-free AHDL module library, including IIC controllers, DRAM controller, UART, etc. 28 modules, source code AHDL
Platform: | Size: 50274 | Author: 董沙瓤 | Hits:

[Embeded-SCM Develop] freecore_ahdl

Description: 免费的AHDL模块库,包括IIC控制器,DRAM控制器,UART等28个模块,AHDL源代码-free AHDL module library, including IIC controllers, DRAM controller, UART, etc. 28 modules, source code AHDL
Platform: | Size: 50176 | Author: | Hits:

[VHDL-FPGA-Verilog] sdr_c_trl_verilog

Description: SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Platform: | Size: 12288 | Author: 曹大壮 | Hits:

[MPI] SRAM_2

Description: FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
Platform: | Size: 553984 | Author: zlw | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 基于FPGA的SDRAM控制器的设计和实现,还比较好勒.-FPGA-based SDRAM controller design and realization, but also better le.
Platform: | Size: 69632 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Platform: | Size: 9216 | Author: 郑宏超 | Hits:

[VHDL-FPGA-Verilog] 61EDA_C52

Description: 标准SDR SDRAM控制器参考设计，有助于大家学习和参考-Standard SDR SDRAM controller reference design will help everyone to learn and reference
Platform: | Size: 205824 | Author: 王廷龙 | Hits:

[Linux-Unix] dram_control

Description: 用vhdl描写的通用异步dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
Platform: | Size: 1024 | Author: wuyub | Hits:

[VHDL-FPGA-Verilog] dram_controller

Description: 用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
Platform: | Size: 1024 | Author: wuyub | Hits:

[Other] Fpgasj

Description: FPGAcpld结构分析 pga的EDA设计方法 fpga中的微程序设计 复杂可编程逻辑器件cpld专题讲座(Ⅴ)──cpld的应用和实现数字逻 一种使用fpga设计的DRAM控制器 用cpld器件实现24位同步计数器的设计-FPGAcpld structural analysis of the EDA design methodology pga of micro-fpga programming complex programmable logic device cpld seminars (Ⅴ) ─ ─ cpld application and realization of digital logic design using fpga with the DRAM controller cpld synchronization devices 24 Counter Design
Platform: | Size: 540672 | Author: 黄诗杰 | Hits:

[VHDL-FPGA-Verilog] dram_cntl

Description: DRAM Controller verilog file
Platform: | Size: 7168 | Author: sachin | Hits:

[Editor] t4

Description: Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
Platform: | Size: 2048 | Author: xxxx | Hits:

[Embeded-SCM Develop] an006

Description: Design of a DRAM Controller
Platform: | Size: 71680 | Author: Aminus | Hits:

[VHDL-FPGA-Verilog] LIP2121CORE_pads_dram_controller

Description: Pads for DRAM CONTROLLER Verilog MODULE
Platform: | Size: 14336 | Author: jc | Hits:

[VHDL-FPGA-Verilog] LIP2131CORE_dram_controller

Description: LIP2131 CORE Verilog DRAM Controller
Platform: | Size: 8136704 | Author: jc | Hits:

[VHDL-FPGA-Verilog] mobile_sdram

Description: mobile DRAM Controller
Platform: | Size: 4096 | Author: gooodman | Hits:

[VHDL-FPGA-Verilog] DDRCHv11

Description: Source code for ddr2 dram controller for BEEE
Platform: | Size: 661504 | Author: shiva | Hits:

[Other] AL422B-user-mannual

Description: The AL422 consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller. -The AL422 consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller.
Platform: | Size: 397312 | Author: liuguoyu | Hits:

[Linux-Unix] mbus

Description: The 4-bit MBUS target ID of the DRAM controller.
Platform: | Size: 1024 | Author: 拿冠军 | Hits:

[VHDL-FPGA-Verilog] sdram controller

Description: Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.
Platform: | Size: 8192 | Author: Robuster | Hits:
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